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LP8733 датащи(PDF) 40 Page - Texas Instruments |
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LP8733 датащи(HTML) 40 Page - Texas Instruments |
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40 / 86 page ![]() START MSB Chip Address LSB ACK from slave ACK from slave ACK from slave SCL SDA START id = 0x60 W ACK address = 0x40 ACK ACK address 0x40 data STOP W ACK MSB Register Address LSB ACK MSB Data LSB ACK STOP SCL SDA tLOW trCL tHD;DAT tHIGH tfCL tSU;DAT tSU;STA tSU;STO START REPEATED START STOP tHD;STA START tSP trDA tBUF tfDA tHD;STA S RS P S 40 LP8733 SNVSBK2 – SEPTEMBER 2019 www.ti.com Product Folder Links: LP8733 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Programming (continued) Figure 25. I2C-Compatible Timing 7.5.1.3 Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8733xx pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8733xx generates an acknowledge after each byte has been received. There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. NOTE If the V(VANA) voltage is below the VANAUVLO threshold level during I 2C communication, the LP8733xx device does not drive SDA line. The ACK signal and data transfer to the master is disabled at that time. After the START condition, the bus master sends a chip address. This address is seven bits long, followed by an eighth bit, which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1 indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. Figure 26. Write Cycle (w = write; SDA = 0). Example Device Address = 0x60 |
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