LP8733 datasheet(54/86 Pages) TI

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LP8733

SNVSBK2 – SEPTEMBER 2019

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Table 31. PG_FAULT Register Field Descriptions

Bits

Field

Type

Default

Description

7:4

Reserved - do not

use

R/W

0000

PG_FAULT_LDO1

R/W

Source for the PGOOD inactive signal:

0 - LDO1 has not set the PGOOD signal inactive.

1 - LDO1 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the LDO1 output is valid.

PG_FAULT_LDO0

R/W

Source for PGOOD inactive signal:

0 - LDO0 has not set the PGOOD signal inactive.

1 - LDO0 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the LDO0 output is valid.

PG_FAULT_BUCK

R/W

Source for PGOOD inactive signal:

0 - Buck1 has not set PGOOD signal inactive.

1 - Buck1 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the Buck1 output is valid.

PG_FAULT_BUCK

R/W

Source for PGOOD inactive signal:

0 - Buck0 has not set PGOOD signal inactive.

1 - Buck0 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the Buck0 output is valid.

7.6.1.25 RESET

RESET is shown in Table 32, Address: 0x18

Figure 53. RESET Register

Reserved - do not use

SW_RESET

Table 32. RESET Register Field Descriptions

Bits

Field

Type

Default

Description

7:1

Reserved - do not

use

R/W

000 0000

SW_RESET

R/W

Software commanded reset. When written to 1, the registers will be reset to the default

values, the OTP memory is read, and the I2C interface is reset.

The bit is automatically cleared.

7.6.1.26 INT_TOP_1

INT_TOP_1 is shown in Table 33, Address: 0x19

Figure 54. INT_TOP_1 Register

PGOOD_INT

LDO_INT

BUCK_INT

SYNC_CLK_IN

TDIE_SD_INT

TDIE_WARN_I

OVP_INT

I_MEAS_INT

Table 33. INT_TOP_1 Register Field Descriptions

Bits

Field

Type

Default

Description

PGOOD_INT

R/W

Latched status bit indicating that the PGOOD pin has changed from active to inactive.

Write 1 to clear interrupt.

LDO_INT

Interrupt indicating that the LDO1 and LDO0 have a pending interrupt. The reason for

the interrupt is indicated in the INT_LDO register.

This bit is cleared automatically when the INT_LDO register is cleared to 0x00.

BUCK_INT

Interrupt indicating that the Buck1 and Buck0 have a pending interrupt. The reason for

the interrupt is indicated in the INT_BUCK register.

This bit is cleared automatically when INT_BUCK register is cleared to 0x00.

SYNC_CLK_INT

R/W

Latched status bit indicating that the external clock has appeared or disappeared.

Write 1 to clear interrupt.

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