XIO2001IPNP datasheet(120/144 Pages) TI

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PCIR

120

XIO2001

SCPS212I – MAY 2009 – REVISED JANUARY 2016

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Typical Application (continued)

Figure 27. 3-State Bidirectional Buffer

9.2.1.2.1.3

Clamping Voltage

In the bridge, the PCI bus I/O drivers are powered from the VDD_33 power rail. Plus, the I/O driver cell is tolerant

to input signals with 5-V peak-to-peak amplitudes.

For PCI bus interfaces operating at 50 MHz or 66 MHz, all devices are required to output only 3.3-V peak-to-

peak signal amplitudes. For PCI bus interfaces operating at 25-MHz or 33-MHz, devices may output either 3.3-V

or 5-V peak-to-peak signal amplitudes. The bridge accommodates both signal amplitudes.

Each PCI bus I/O driver cell has a clamping diode connected to the internal VCCP voltage rail that protects the

cell from excessive input voltage. The internal VCCP rail is connected to two PCIR terminals. If the PCI signaling

is 3.3-V, then PCIR terminals are connected to a 3.3-V power supply via a 1-k

Ω resistor. If the PCI signaling is 5-

V, then the PCIR terminals are connected to a 5-V power supply via a 1k

Ω resistor.

The PCI bus signals attached to the VCCP clamping voltage are identified as follows

•

Pin Functions table, PCI System Terminals, all terminal names except for PME

•

Pin Functions table, Miscellaneous Terminals, the terminal name SERIRQ.

9.2.1.2.1.4

PCI Bus Clock Run

The bridge supports the clock run protocol as specified in the PCI Mobile Design Guide. When the clock run

protocol is enabled, the bridge assumes the role of the central resource master.

To enable the clock run function, terminal CLKRUN_EN is asserted high. Then, terminal GPIO0 is enabled as the

CLKRUN signal. An external pullup resistor must be provided to prevent the CLKRUN signal from floating To

verify the operational status of the PCI bus clocks, bit 0 (SEC_CLK_STATUS) in the clock run status register at

offset DAh (see Clock Run Status Register) is read.

Since the bridge has several unique features associated with the PCI bus interface, the system designer must

consider the following interdependencies between these features and the CLKRUN feature:

1. If the system designer chooses to generate the PCI bus clock externally, then the CLKRUN mode of the

bridge must be disabled. The central resource function within the bridge only operates as a CLKRUN master

and does not support the CLKRUN slave mode.

2. If the central resource function has stopped the PCI bus clocks, then the bridge still detects INTx state

changes and will generate and send PCI Express messages upstream.

3. If the serial IRQ interface is enabled and the central resource function has stopped the PCI bus clocks, then

any PCI bus device that needs to report an IRQ interrupt asserts CLKRUN to start the bus clocks.

4. When a PCI bus device asserts CLKRUN, the central resource function turns on PCI bus clocks for a

minimum of 512 cycles.

5. If the serial IRQ function detects an IRQ interrupt, then the central resource function keeps the PCI bus

clocks running until the IRQ interrupt is cleared by software.

6. If the central resource function has stopped the PCI bus clocks and the bridge receives a downstream

transaction that is forwarded to the PCI bus interface, then the bridge asserts CLKRUN to start the bus

clocks.

7. The central resource function is reset by PCI bus reset (PRST) assuring that clocks are present during PCI

bus resets.

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