XIO2001IPNP datasheet(118/144 Pages) TI

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118

XIO2001

SCPS212I – MAY 2009 – REVISED JANUARY 2016

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Typical Application (continued)

•

SERIRQ is an optional PCI bus signal. When PERST is de-asserted, if a pullup resistor to VCCP is detected

on terminal M08, the serial IRQ interface is enabled. A pulldown resistor to V SS disables this feature. If

SERIRQ is present in a system, it is connected to each PCI bus device that supports the feature and must

meet PCI bus loading requirements for the selected clock frequency. An approved PCI bus pullup resistor to

VCCP is required to keep this signal from floating. SERIRQ is a bused signal and synchronous to the PCI bus

clock. All synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.

NOTE

SERIRQ does not support serialized PCI interrupts and is used for serializing the 16 ISA

interrupts.

•

CLKRUN is an optional PCI bus signal that is shared with the GPIO0 pin. When PERST is de-asserted and if

a pullup resistor to VDD_33 is detected on pin C11 (CLKRUN_EN), the clock run feature is enabled. If CLKRUN

is required in a system, this pin is connected to each PCI bus device and must meet PCI bus loading

requirements for the selected clock frequency. An approved PCI bus pullup resistor to VDD_33 is required per

the PCI Mobile Design Guide . CLKRUN is a bused signal and synchronous to the PCI bus clock. All

synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.

NOTE

If CLKRUN is used in a system, it must be supported by all devices attached to the PCI

bus; if a device that does not support CLKRUN is attached to a bus where it is enabled,

there is a danger that it will not be able to have a clock when it requires one.

•

PWR_OVRD is an optional PCI bus signal that is shared with the GPIO1 terminal. In PWR_OVRD mode, this

pin is always an output and is asynchronous to the PCI bus clock. When the power override control bits in the

general control register at offset D4h are set to 001b or 011b, the M09 pin operates as the PWR_OVRD

signal. Prior to setting the power override control bits, the GPIO1 // PWR_OVRD pin defaults to a standard

GPIO pin.

•

PME is an optional PCI bus input terminal to detect power management events from downstream devices.

The PME terminal is operational during both main power states and VAUX states. The PME receiver has

hysteresis and expects an asynchronous input signal. The board design requirements associated with this

PME terminal are the same whether or not the terminal is connected to a downstream device. If the system

includes a VAUX supply, the PME terminal requires a weak pullup resistor connected to VAUX to keep the

terminal from floating. If no VAUX supply is present, the pullup resistor is connected to VDD_33.

•

The bridge supports external PCI bus clock sources. If an external clock is a system requirement, the external

clock source is connected to the CLK terminal. The trace length relationship between the synchronous bus

signals and the external clock signals that is previously described is still required to meet PCI bus setup and

hold. For external clock mode, all seven CLKOUT[6:0] terminals can be disabled using the clock control

because there is no method of turning off external clocks.

NOTE

If an external clock with a frequency higher than 33 MHz is used, the M66EN terminal

must be pulled up for the XIO2001 to function correctly.

•

The XIO2001 supports an external PCI bus arbiter. When PERST is deasserted, the logic state of the

EXT_ARB_EN pin is checked. If an external arbiter is required, EXT_ARB_EN is connected to VDD_33. When

connecting the XIO2001 to an external arbiter, the external arbiter’s REQ signal is connected to the XIO2001

0 GNT output terminal. Likewise, the GNT signal from the external arbiter is connected to the XIO2001 0

REQ input pin. Unused REQ signals on the XIO2001 should be tied together and connected to VCCP through

a pull-up resistor. When in external arbiter mode, all internal XIO2001 port arbitration features are disabled.

Figure 26 illustrates the connectivity of an external arbiter.

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