XIO2001IPNP datasheet(40/144 Pages) TI

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XIO2001

SCPS212I – MAY 2009 – REVISED JANUARY 2016

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To access the serial EEPROM through the software interface, the following steps are performed:

1. The control and status byte is read to verify the EEPROM interface is enabled (SBDETECT asserted) and

not busy (REQBUSY and ROMBUSY deasserted).

2. The serial-bus word address is loaded. If the access is a write, then the data byte is also loaded.

3. The serial-bus slave address and R/W command selector byte is written.

4. REQBUSY is monitored until this bit is deasserted.

5. SB_ERR is checked to verify that the serial-bus operation completed without error. If the operation is a read,

then the serial-bus data byte is now valid.

8.3.9 Advanced Error Reporting Registers

In the extended PCI Express configuration space, the bridge supports the advanced error reporting capabilities

structure. For the PCI Express interface, both correctable and uncorrectable error statuses are provided. For the

PCI bus interface, secondary uncorrectable error status is provided. All uncorrectable status bits have

corresponding mask and severity control bits. For correctable status bits, only mask bits are provided.

Both the primary and secondary interfaces include first error pointer and header log registers. When the first error

is detected, the corresponding bit position within the uncorrectable status register is loaded into the first error

pointer register. Likewise, the header information associated with the first failing transaction is loaded into the

header log. To reset this first error control logic, the corresponding status bit in the uncorrectable status register

is cleared by a writeback of 1b.

For systems that require high data reliability, ECRC is fully supported on the PCI Express interface. The primary

side advanced error capabilities and control register has both ECRC generation and checking enable control bits.

When the checking bit is asserted, all received TLPs are checked for a valid ECRC field. If the generation bit is

asserted, then all transmitted TLPs contain a valid ECRC field.

8.3.10 Data Error Forwarding Capability

The bridge supports the transfer of data errors in both directions.

If a downstream PCI Express transaction with a data payload is received that targets the internal PCI bus and

the EP bit is set indicating poisoned data, then the bridge must ensure that this information is transferred to the

PCI bus. To do this, the bridge forces a parity error on each PCI bus data phase by inverting the parity bit

calculated for each double-word of data.

If the bridge is the target of a PCI transaction that is forwarded to the PCI Express interface and a data parity

error is detected, then this information is passed to the PCI Express interface. To do this, the bridge sets the EP

bit in the upstream PCI Express header.

8.3.11 General-Purpose I/O Interface

Up to five general-purpose input/output (GPIO) terminals are provided for system customization. These GPIO

terminals are 3.3-V tolerant.

The exact number of GPIO terminals varies based on implementing the clock run, power override, and serial

EEPROM interface features. These features share four of the five GPIO terminals. When any of the three shared

functions are enabled, the associated GPIO terminal is disabled.

All five GPIO terminals are individually configurable as either inputs or outputs by writing the corresponding bit in

the GPIO control register at offset B4h (See GPIO Control Register). A GPIO data register at offset B6h exists to

either read the logic state of each GPIO input or to set the logic state of each GPIO output. The power-up default

state for the GPIO control register is input mode.

8.3.12 Set Slot Power Limit Functionality

The PCI Express Specification provides a method for devices to limit internal functionality and save power based

on the value programmed into the captured slot power limit scale (CSPLS) and capture slot power limit value

(CSPLV) fields of the PCI Express device capabilities register at offset 74h. See Device Capabilities Register,

Device Capabilities Register, for details. The bridge writes these fields when a set slot power limit message is

received on the PCI Express interface.

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