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XIO2001IPNP датащи(PDF) 37 Page - Texas Instruments

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номер детали XIO2001IPNP
подробное описание детали  XIO2001 PCI Express to PCI Bus Translation Bridge
PDF  144 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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XIO2001IPNP датащи(HTML) 37 Page - Texas Instruments

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SCL From
Master
1
2
3
7
8
9
SDA Output
By Transmitter
SDA Output
By Receiver
37
XIO2001
www.ti.com
SCPS212I – MAY 2009 – REVISED JANUARY 2016
Product Folder Links: XIO2001
Submit Documentation Feedback
Copyright © 2009–2016, Texas Instruments Incorporated
Figure 20. Serial-Bus Protocol Acknowledge
The bridge performs three basic serial-bus operations: single byte reads, single byte writes, and multibyte reads.
The single byte operations occur under software control. The multibyte read operations are performed by the
serial EEPROM initialization circuitry immediately after a PCI Express reset. See Serial-Bus EEPROM
Application, Serial-Bus EEPROM Application, for details on how the bridge automatically loads the subsystem
identification and other register defaults from the serial-bus EEPROM.
Figure 21 illustrates a single byte write. The bridge issues a start condition and sends the 7-bit slave device
address and the R/W command bit is equal to 0b. A 0b in the R/W command bit indicates that the data transfer is
a write. The slave device acknowledges if it recognizes the slave address. If no acknowledgment is received by
the bridge, then bit 1 (SB_ERR) is set in the serial-bus control and status register (PCI offset B3h, see Serial-Bus
Control and Status Register). Next, the EEPROM word address is sent by the bridge, and another slave
acknowledgment is expected. Then the bridge delivers the data byte MSB first and expects a final
acknowledgment before issuing the stop condition.
Figure 21. Serial-Bus Protocol – Byte Write
Figure 22 illustrates a single byte read. The bridge issues a start condition and sends the 7-bit slave device
address and the R/W command bit is equal to 0b (write). The slave device acknowledges if it recognizes the
slave address. Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment is
expected. Then, the bridge issues a restart condition followed by the 7-bit slave address and the R/W command
bit is equal to 1b (read). Once again, the slave device responds with an acknowledge. Next, the slave device
sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the bridge responds with no acknowledge (logic
high) indicating the last data byte. Finally, the bridge issues a stop condition.
Figure 22. Serial-Bus Protocol – Byte Read



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