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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XIO2001IPNP датащи(PDF) 54 Page - Texas Instruments |
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XIO2001IPNP датащи(HTML) 54 Page - Texas Instruments |
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54 / 144 page  54 XIO2001 SCPS212I – MAY 2009 – REVISED JANUARY 2016 www.ti.com Product Folder Links: XIO2001 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated 8.4.24 Prefetchable Limit Upper 32-Bit Register This read/write register specifies the upper 32 bits of the prefetchable memory limit register. See Table 24 for a complete description of the register contents. PCI register offset: 2Ch Register type: Read/Write Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 24. Prefetchable Limit Upper 32-Bit Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:0 PRELIMIT RW Prefetchable memory limit upper 32 bits. Defines the upper 32 bits of the highest address of the prefetchable memory address range that determines when to forward memory transactions downstream. 8.4.25 I/O Base Upper 16-Bit Register This read/write register specifies the upper 16 bits of the I/O base register. See Table 25 for a complete description of the register contents. PCI register offset: 30h Register type: Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25. I/O Base Upper 16-Bit Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:0 IOBASE RW I/O base upper 16 bits. Defines the upper 16 bits of the lowest address of the I/O address range that determines when to forward I/O transactions downstream. These bits correspond to address bits [31:20] in the I/O address. The lower 20 bits are assumed to be 00000h. 8.4.26 I/O Limit Upper 16-Bit Register This read/write register specifies the upper 16 bits of the I/O limit register. See Table 26 for a complete description of the register contents. PCI register offset: 32h Register type: Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
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