XIO2001IPNP datasheet(124/144 Pages) TI

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XIO2001

SCPS212I – MAY 2009 – REVISED JANUARY 2016

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9.2.4.1 Design Requirements

See previous Design Requirements.

9.2.4.2 Detailed Design Procedure

See previous Detailed Design Procedure.

9.2.5 Power Filtering

Figure 31. Power Filtering

9.2.5.1 Design Requirements

See previous Design Requirements.

9.2.5.2 Detailed Design Procedure

See previous Detailed Design Procedure.

9.3 Layout

9.3.1 Layout Guidelines

In motherboard designs there is an additional clock delay on the PCI add-in cards. In order to make the overall

lengths of the PCI Clock Signals be the same, a rule has been made, which states that the length of the Clock

Signal will be fixed to 2.5" on PCI add-in cards. The motherboard design requires that the length of the Clock

Signal going to the PCI add-in slots will be less by 2.5" in comparison with the other Clock Signals that do not go

to a PCI add-in slot. With the PCI add-in cards inserted, the Clock Signals lengths match. In a design where

there is no add-in slot, the length of the PCI Clock Signals should match. A typical embedded system has all PCI

devices on the board itself. In such case, the lengths of clock nets should match.

There is no matching requirement on the length of the Address/Data signals with respect to Clock Signal, though,

there is a limitation on the maximum length of the Address/Data signal length depending upon the PCI Bus

speed. The length matching of clock signals in PCI bus is not very critical. It is however, often, not too difficult to

match it within 100 mils. The PCI Clock Signals should be slightly longer than the longest trace on the PCI bus.

When 100 mil recommendations become impractical due to board space constraints, this can be relaxed up to a

recommended maximum of 250 mils.

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