XIO2001IPNP datasheet(116/144 Pages) TI

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XIO2001

SCPS212I – MAY 2009 – REVISED JANUARY 2016

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Typical Application (continued)

The selection of bulk capacitors with low-ESR specifications is recommended to minimize low-frequency power

supply noise. Today, the best low-ESR bulk capacitors are radial leaded aluminum electrolytic capacitors. These

capacitors typically have ESR specifications that are less than 0.01

Ω at 100 kHz. Also, several manufacturers

sell “ D ” size surface mount specialty polymer solid aluminum electrolytic capacitors with ESR specifications

slightly higher than 0.01

Ω at 100 kHz. Both of these bulk capacitor options significantly reduce low-frequency

power supply noise and ripple.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1

PCI Bus Interface

The XIO2001 has a 32-bit PCI interface that can operate at 25 MHz, 33 MHz, 50 MHz or 66 MHz. This interface

is compliant with the PCI Local Bus Specification , Revision 2.3 and 3.0. The remainder of this section describes

implementation considerations for the XIO2001 secondary PCI bus interface.

•

AD31:0, C/BE[3:0], PAR, DEVSEL, FRAME, STOP, TRDY, PERR, SERR, and IRDY are required signals and

must be connected to each PCI bus device. The maximum signal loading specification for a 66 MHz bus is 30

pF and for a 33 MHz bus is 50 pF. PCI bus approved pullup resistors connected to VCCP are needed on the

following terminals: IRDY, TRDY, FRAME, STOP, PERR, SERR, and DEVSEL.

•

The XIO2001 supports up to six external PCI bus devices with individual CLKOUT, REQ, and GNT signals.

An internal PCI bus clock generator function provides six low-skew clock outputs. Plus, there are six REQ

inputs and six GNT outputs from the internal PCI bus arbiter. Each PCI bus device connects to one CLKOUT

signal, one REQ signal, and one GNT signal. All three signals are point-to- point connections. Unused

CLKOUT signals can be disabled by asserting the appropriate CLOCK_DISABLE bit in the clock control

GNT signals are no connects.

•

An external clock feedback feature is provided to de-skew PCI bus clocks. Connecting the CLKOUT[6]

terminal to the CLK terminal is required if any of the other six CLKOUT[5:0] terminals are used to clock PCI

bus devices. The CLKOUT signals should be slightly longer than the longest synchronous PCI bus signal

trace. Figure 25 illustrates the external PCI bus clock feedback feature. The use of series resistors on the

seven PCI bus clocks should be considered to reduce circuit board EMI.

NOTE

There is one exception to this length matching rule associated with connecting a CLKOUT

signal to PCI socket. For this case, the CLKOUT signal connected to a PCI socket should

be 2.5 inches shorter than the other CLKOUT signals.

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