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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XIO2001IPNP датащи(PDF) 30 Page - Texas Instruments |
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XIO2001IPNP датащи(HTML) 30 Page - Texas Instruments |
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30 / 144 page  30 XIO2001 SCPS212I – MAY 2009 – REVISED JANUARY 2016 www.ti.com Product Folder Links: XIO2001 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated 8.3.2.6 Wake PCI Express WAKE is an open-drain output from the XIO2001 that is driven low to re-activate the PCI Express link hierarchy’s main power rails and reference clocks. This PCI Express side-band signal is connected to the WAKE input on the upstream PCIe device. WAKE is operational during both the main power state and VAUX power state. Since WAKE is an open-drain output, a system side pullup resistor is required to prevent the signal from floating. The drive capability of this open-drain output is 4 mA. Therefore, the value of the selected pullup resistor must be large enough to assure a logic low signal level at the receiver. A robust system design will select a pullup resistor value that de-rates the output driver current capability by a minimum of 50%. At 3.3 V with a de-rated drive current equal to 2 mA, the minimum resistor value is 1.65 k Ω . Larger resistor values are recommended to reduce the current drain on the VAUX supply. 8.3.2.7 Initial Flow Control Credits The bridge flow control credits are initialized using the rules defined in the PCI Express Base Specification. Table 3 identifies the initial flow control credit advertisement for the bridge. Table 3. Initial Flow Control Credit Advertisements CREDIT TYPE INITIAL ADVERTISEMENT Posted request headers (PH) 8 Posted request data (PD) 128 Non-posted header (NPH) 4 Non-posted data (NPD) 4 Completion header (CPLH) 0 (infinite) Completion data (CPLD) 0 (infinite) 8.3.2.8 PCI Express Message Transactions PCI Express messages are both initiated and received by the bridge. Table 4 outlines message support within the bridge. Table 4. Messages Supported by the Bridge MESSAGE SUPPORTED BRIDGE ACTION Assert_INTx Yes Transmitted upstream Deassert_INTx Yes Transmitted upstream PM_Active_State_Nak Yes Received and processed PM_PME Yes Transmitted upstream PME_Turn_Off Yes Received and processed PME_TO_Ack Yes Transmitted upstream ERR_COR Yes Transmitted upstream ERR_NONFATAL Yes Transmitted upstream ERR_FATAL Yes Transmitted upstream Set_Slot_Power_Limit Yes Received and processed Unlock No Discarded Hot plug messages No Discarded Advanced switching messages No Discarded Vendor defined type 0 No Unsupported request Vendor defined type 1 No Discarded All supported message transactions are processed per the PCI Express Base Specification. 8.3.3 PCI Port Arbitration The internal PCI port arbitration logic supports up to six external PCI bus devices plus the bridge. This bridge supports a classic PCI arbiter. |
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