XIO2001IPNP datasheet(117/144 Pages) TI

117 / 144 page

XIO2001

VCCP

PCI Device

PCI Bus

M66EN pullup resistor enables

50/66 MHz by default.

Pulldown used if bus is known

to be 25/33 M z.

CLKOUT0

PCLK66_SEL

M66EN

CLK

CLKOUT6

CLKOUT[5:1]

Feedback clock from CLKOUT6

should be slightly longer than

the longest CLK provided to a

downstream device. A 50

dampening resistor can be

used to reduce reflection.

Unused PCI clocks can be left

floating and disabled via PCI

power and noise.

When connected to add-in

card slots, 33 MHz cards will

force M66EN to ground to

indicate 33 M z only

operation.

When pulled high, standard

33/66 MHz clocks are

provided (based on M66EN).

When pulled low 25/50 MHz

clocks are provided (based on

M66EN).

117

XIO2001

www.ti.com

SCPS212I – MAY 2009 – REVISED JANUARY 2016

Product Folder Links: XIO2001

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Typical Application (continued)

Figure 25. External PCI Bus Clock Configuration

•

The XIO2001 has options providing for four different PCI clock frequencies: 25 MHz, 33 MHz, 50 MHz, and

66MHz. The clock frequency provided is determined by the states of the M66EN and PCLK66_SEL terminals

at the de-assertion of PERST.

•

The PCLK66_SEL terminal determines if the XIO2001 provides either the standard 33/66 MHz frequencies or

25/50 MHz frequencies. If this terminal is pulled high at the de-assertion of PERST, then CLKOUTx terminals

provide the standard PCI 33/66 MHz frequencies (depending on the state of M66EN). If the terminal is pulled

low at the de-assertion of PERST, then a 25/50 MHz frequency is provided instead. The determination of

what frequency to use is design-specific, and this terminal must be pulled high or low appropriately.

•

The M66EN terminal determines if the PCI Bus will operate at low speed (50/25 MHz) or high speed (66/33

MHz). At the de-assertion of PERST, the M66EN terminal is checked and if it is pulled to VCCP, then the high-

speed (66 MHz or 50 MHz) frequencies are used. If the pin is low, then the low-speed (33 MHz or 25 MHz)

frequencies are used. If the speed of all devices attached to the PCI bus is known, then this terminal can be

pulled appropriately to set the speed of the PCI bus. If add-in card slots are present on a high-speed bus that

may have low speed devices attached, then the terminal can be pulled high and connected to the slot,

permitting the add-in card to pull the terminal low and reduce the bus speed if a low-speed card is inserted.

•

IDSEL for each PCI bus device must be resistively coupled (100

Ω) to one of the address lines between

AD31 and AD16. Please refer to the XIO2001 Data Manual for the configuration register transaction device

number to AD bit translation chart.

•

PCI interrupts can be routed to the INT[D:A] inputs on the XIO2001. These four inputs are asynchronous to

the PCI bus clock and will detect state changes even if the PCI bus clock is stopped. For each INT[D:A] input,

an approved PCI bus pullup resistor to VCCP is required to keep each interrupt signal from floating. Interrupts

on the XIO2001 that are not connected to any device may be tied together and pulled-up through a single

resistor.

•

PRST is a required PCI bus signal and must be connected to all devices. This output signal is asynchronous

to the PCI bus clock. Since the output driver is always enabled and either driving high or low, no pullup

resistor is needed.

•

LOCK is an optional PCI bus signal. If LOCK is present in a system, it is connected to each PCI bus device

that supports the feature and must meet PCI bus loading requirements for the selected clock frequency. An

approved PCI bus pullup resistor to VCCP is required to keep this signal from floating, even if it is not

connected to devices on the bus. LOCK is a bused signal and synchronous to the PCI bus clock. All

synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.

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