UPD360 datasheet(136/221 Pages) MICROCHIP

136 / 221 page

UPD360

DS00002084C-page 136

 2016-2017 Microchip Technology Inc.

TX_HARD_RESET

Setting this bit to 1 together with the GO bit will cause hardware configured for

Auto Mode data processing to transmit a Hard Reset. Any data in the TX

Queue and related registers is ignored.

This bit is not applicable to Raw Mode data processing since a Hard Reset

packet can be explicitly specified in the TX Queue. It is ignored for Raw Mode.

This bit can only be set if the GO bit is not currently set.

This bit is cleared by hardware at end of packet transmission. This bit is reset

by assertion of PD_RESET. Software can only write 1 to this bit and therefore

can not clear it once set.

Note:

Hard Reset is not automatically retried (there is no feedback to indi-

cate a failure). It is up to software to perform Hard Reset retries.

Note:

This bit will be cleared upon completion of any packet transmis-

sion, so it should be set only after the GO bit is cleared after com-

pletion of the prior transmission.

W1S/SC

ABORT

Setting this bit will abort the current transmission in progress as soon as pos-

sible. Writing a '0' has not effect.

Hardware does not latch this bit and it will read back as zero.

Hardware will finish the current nibble transmission, send EOP, and then ter-

minate transmission. If this bit is set during preamble phase, then the current

bit of the preamble will be completed prior to termination.

Software should use the TX_EOP status bit in the TX Interrupt Status Register

(TX_IRQ_STAT) to determine when the current packet has been terminated.

Writing a 1 to this bit will:

• Start transmission of the packet in the TX queue on to the wire or:

• Send Hard Reset if the TX_HARD_RESET bit of this register is set and

data processing mode is set to Auto (i.e., the EN_RMDP bit in the TX

Control Register A (TX_CTL_A) is not set).

• Send Cable Reset if the TX_CABLE_RESET bit of this register is set and

data processing mode is set to Auto (i.e., the EN_RMDP bit in the TX

Control Register A (TX_CTL_A) is not set).

Hardware will clear this bit when transmission is complete. This bit is reset by

assertion of PD_RESET. Software can only write 1 to this bit and therefore

can not clear it once set. Clearing of this bit by hardware does not indicate the

message was sent successfully.

Hardware may detect bus collision and abort transmission. In this case, the

TX_ABORTED bit in the TX Interrupt Status Register (TX_IRQ_STAT) will be

set and an interrupt to MCU will be generated.

W1S/SC

Bits

Description

Type

Default

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