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UPD360 датащи(PDF) 135 Page - Microchip Technology |
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UPD360 датащи(HTML) 135 Page - Microchip Technology |
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135 / 221 page ![]() 2016-2017 Microchip Technology Inc. DS00002084C-page 135 UPD360 11.4.1.6 TX Control Register B (TX_CTL_B) Address: 1A05h Size: 8 bits Bits Description Type Default 7:6 RESERVED RO - 5 TX_CABLE_RESET Setting this bit to 1 together with the GO bit will cause hardware configured for Auto Mode data processing to transmit a Cable Reset. Any data in the TX Queue and related registers is ignored. This bit is not applicable to Raw Mode data processing since Cable Reset packets can be explicitly specified in the TX Queue. It is ignored for Raw Mode. This bit can only be set if the GO bit is not currently set. The TX_HARD_RESET bit has precedence and if set along with this bit, this bit will not set. This bit is cleared by hardware at end of packet transmission. This bit is reset by assertion of PD_RESET. Software can only write 1 to this bit and therefore can not clear it once set. Note: Cable Reset is not automatically retried (there is no feedback to indicate a failure). It is up to software to perform Cable Reset retries. Note: This bit will be cleared upon completion of any packet transmis- sion, so it should be set only after GO bit is cleared after completion of the prior transmission. W1S/SC 0b 4 OK_TO_TX Channel is idle and it is OK to transmit. Software should monitor this bit before setting the GO bit. 0: Software should not set the GO bit 1: Software can set the GO bit. The following conditions will cause hardware to set this bit to 0: • BMC line idle timer indicating line is busy. • Hardware may be processing an automatic response to a received packet. RO 1b 3 RST_TXQ_FIFO_WRI_PTR Setting this bit will reset the TX Queue's write interface FIFO pointer. When using FIFO Mode Queuing, software must always write a '1' to this bit prior to putting data in the FIFO. Hardware does not latch this bit and it will read back as zero. Hardware may automatically reset the pointer when the GO bit is cleared (i.e., hardware is done with current transmission). WO 0b |
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