UPD360 datasheet(211/221 Pages) MICROCHIP

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 2016-2017 Microchip Technology Inc.

DS00002084C-page 211

UPD360

Note 16-4

tVD;ACK = time for Acknowledgment signal from I2C_CLK LOW to I2C_DAT (out) LOW.

Note 16-5

tVD;DAT = minimum time for I2C_DAT data out to be valid following I2C_CLK LOW.

Note 16-6

A master device must internally provide a hold time of at least 300 ns for the I2C_DAT signal (refer

to the VIL of the I2C_CLK signal) in order to bridge the undefined region I2C_CLK‘s falling edge.

Note 16-7

The maximum tf for the I2C_DAT and I2C_CLK bus lines is specified at 300 ns. The maximum fall

time for the I2C_DAT output stage tf is specified at 250 ns. This allows series protection resistors to

be connected between the I2C_DAT and I2C_CLK pins and the respective bus lines without

exceeding the maximum specified tf.

Note 16-8

Input filters on the I2C_DAT and I2C_CLK inputs suppress noise spikes less than 50 ns.

16.6.3

SPI SLAVE INTERFACE (UPD360-C ONLY)

Figure 16-4 and Figure 16-5 illustrate the SPI slave interface input and output timing requirements, respectively. Refer

to Section 6.0, "SPI Slave Controller (UPD360-C Only)," on page 26 for additional information.

TABLE 16-10: I2C SLAVE TIMING VALUES

Symbol

Description

Min

Max

Units

fCLK

I2C_CLK clock frequency

1000

kHz

tBUF

Bus free time between a STOP and START condition

0.5

s

tHD;STA

Hold time (repeated) START condition

0.26

s

tSU;STA

Setup time for repeated START condition

0.26

s

tSU;STO

Setup time for STOP condition

0.26

s

tHD;DAT

Data hold time

tVD;ACK

Data valid acknowledge time (Note 16-4)

0.05

0.45

s

tVD;DAT

Data valid time (Note 16-5)

450

tSU;DAT

Data setup time

tLOW

LOW period of the I2C_CLK clock

0.5

s

tHIGH

HIGH period of the I2C_CLK clock

0.26

s

Fall time of I2C_CLK and I2C_DAT

(Note 16-6)(Note 16-7)

120

Rise time of I2C_CLK and I2C_DAT

(Note 16-6)(Note 16-7)

120

tSP

Pulse width of spikes that must be suppressed by the input filter

(Note 16-8)

FIGURE 16-4:

SPI SLAVE INPUT TIMING

SPI_CLK

SPI_DI

SPI_CS

tscss

thigh

tlow

tsu

thd

tscshl

tscsh

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