UPD360 datasheet(203/221 Pages) MICROCHIP

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DS00002084C-page 203

UPD360

15.4

Watchdog Timer Registers

This section details the watchdog timer registers. For an overview of the entire device register map, refer to Section 4.0,

"Register Map," on page 19.

15.4.1

WATCHDOG CONTROL REGISTER (WDT_CTL)

Note 15-1

Default value depends on whether a WDT initiated reset occurred, in which the case the value is 1b.

Otherwise the value is 0b.

TABLE 15-1:

WATCHDOG TIMER REGISTER MAP

Address

3000h

Watchdog Control Register (WDT_CTL)

3002h

Watchdog Kick Register (WDT_KICK)

3004h

Watchdog Count Register (WDT_COUNT)

3008h

Watchdog Load Register (WDT_LOAD)

300Ch – 33FFh

Reserved for future expansion

Note:

RESERVED address space must not be written under any circumstances. Failure to heed this warn-

ing may result in untoward operation and unexpected results.

Address:

3000h

Size:

16 bits

Bits

Description

Type

Default

15:4

RESERVED

WDT_UNITS

0: Units of 1 ms are used.

1: Units of 1 us are used.

Note:

When units of 1 us are used, the 48 MHz Relaxation Oscillator

must be enabled and device current consumption will increase by

over 400 uA. Otherwise, when units are 1 ms, the 20 KHz Keep

Alive Oscillator is used.

R/W

WDT_SIM

Used for speeding up the watchdog timer for simulation. Watchdog operates

off of a 1 MHz clock when set.

When this bit is set, WDT_UNITS shall be set to 1b.

R/W

WDT_STS

WDT Status is set by hardware if the last reset of the device was caused by an

underflow of the WDT. This bit must be cleared by software writing a ‘1’ to this

bit. Writing a ‘0’ to this bit has no effect.

R/WC

Note 15-1

WDT_EN

When set, the watchdog timer is enabled. Clearing this bit disables the watch-

dog timer.

Note:

Due to clock domain synchronization, several clock cycles may

elapse before this takes affect and the WDT counter begins to dec-

rement.

R/W

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