UPD360 datasheet(196/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 196

 2016-2017 Microchip Technology Inc.

When an Hot Plug event occurs, the HPD Event Queue Register (HPD_QUEUE) is updated and an interrupt will

assert if configured.

HPD state changes are reflected by assertion of QUEUE_NOT_EMPTY, HPD_HIGH, HPD_LOW and IRQ_HPD

bits in HPD Interrupt Status Register (HPD_INT_STS). They may cause assertion of HPD_INT in the Interrupt

Status Register (INT_STS), if enabled.

Software reads the HPD Event Queue Register (HPD_QUEUE) to determine the Hot Plug events received.

Software writes to the HPD Event Queue Register (HPD_QUEUE) and clears the valid entries.

14.3

HPD Transmission

The device provides HPD transmission (output) via the HPD pin. This is done via the HPD Control Register (HPD_CTL)

by setting both HPD Configuration and HPD Enable to “1”. The value driven on the HPD pin is controlled by HPD Output

Value.

Support is also provided for generating an IRQ_HPD. This is accomplished by programming the deassertion time in

HPD IRQ Generation Time Register (HPD_IRQ_GEN) and then setting Generate IRQ in HPD Control Register

(HPD_CTL). Generate IRQ self clears after the interrupt pulse is issued.

This feature is used as follows:

Configure the HPD pin as an output by setting HPD Configuration and HPD Enable in HPD Control Register

(HPD_CTL). The value for HPD is defined by the value programmed in HPD Output Value.

If it is desired to generate an IRQ_HPD, the HPD IRQ Generation Time Register (HPD_IRQ_GEN) must be pro-

grammed with the desired HPD deassertion time.

If it is desired to receive an interrupt upon generation of IRQ_HPD, the respective bit in the HPD Interrupt Enable

Software requests IRQ_HPD generation by setting Generate IRQ in the HPD Control Register (HPD_CTL). HPD

Output Value must also be set to 1b.

Upon generating the IRQ_HPD interrupt, the Generate IRQ bit will self clear.

The IRQ_HPD bit asserts in the HPD Interrupt Status Register (HPD_INT_STS) and shall cause assertion of the

HPD_INT interrupt in the Interrupt Status Register (INT_STS), if enabled.

14.4

DisplayPort HPD Registers

This section details the DisplayPort HPD registers. For an overview of the entire device register map, refer to Section

4.0, "Register Map," on page 19.

TABLE 14-1:

DISPLAYPORT HPD REGISTER MAP

Address

0C00h

HPD Control Register (HPD_CTL)

0C01h

HPD Interrupt Status Register (HPD_INT_STS)

0C02h

HPD Interrupt Enable Register (HPD_INT_EN)

0C03h

HPD Event Queue Register (HPD_QUEUE)

0C04h

IRQ_HPD Minimum Time Register (IRQ_HPD_MIN_TIME)

0C05h

IRQ_HPD Maximum Time Register (IRQ_HPD_MAX_TIME)

0C06h

HPD High Detect Time Register (HPD_HIGH_DET_TIME)

0C08h

HPD Low Detect Time Register (HPD_LOW_DET_TIME)

0C0Ah

HPD IRQ Generation Time Register (HPD_IRQ_GEN)

0C0Bh – 0FFFh

Reserved for future expansion

Note:

RESERVED address space must not be written under any circumstances. Failure to heed this warn-

ing may result in untoward operation and unexpected results.

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