VSC7511 datasheet(73/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

The following table lists the registers associated with aggregation code generation.

The classifier generates a link aggregation code, which is used in the analyzer when selecting to which

port in a link aggregation group a frame is forwarded.

The following contributions to the link aggregation code is configured in the AGGR_CFG register:

•

Destination MAC address—use the lower 12 bits of the DMAC.

•

Source MAC address—use the lower 12 bits of the SMAC.

•

IPv6 flow label—use the 20 bits of the flow label.

•

IPv4 source and destination IP addresses—use the lower 8 bits of the SIP and DIP.

•

TCP/UDP source and destination port for IPv4 and IPv6 frames—use the lower 8 bits of the SPORT

and DPORT.

•

Random aggregation code—use a pseudo-random number instead of the frame information.

Each of the enabled contributions are XOR’ed together, yielding a 4-bit aggregation code ranging from 0

to 15. For more information about how the aggregation code is used, see Link Aggregation, page 246.

3.7.6

CPU Forwarding Determination

The following table lists the registers associated with CPU forwarding in the basic classifier.

The classifier has support for determining whether certain frames must be forwarded to the CPU

extraction queues. Other parts of the device can also determine CPU forwarding, for example, the

analyzer or the VCAP IS2. All events leading to CPU forwarding are OR’ed together, and the final CPU

extraction queue mask, which is available to the user, contains the sum of all events leading to CPU

extraction. For more information, see CPU Extraction and Injection, page 263.

Upon CPU forwarding by the classifier, the frame type determines whether the frame is redirected or

copied to the CPU. Any frame type or event causing a redirection to the CPU cause all front ports to be

removed from the forwarding decision - only the CPU receives the frame. When copying a frame to the

CPU, the normal forwarding of the frame is unaffected.

Table 30 •

Aggregation Code Generation Registers

Description

Replication

ANA::AGGR_CFG

Configures use of Layer-2 through Layer-4 flow

information for link aggregation code generation.

Common

Table 31 •

CPU Forwarding Determination

Description

Replication

CPU_FWD_CFG

Enables CPU forwarding for various frame types.

Per port

CPU_FWD_BPDU_CFG

Enables CPU forwarding per BPDU address.

Per port

CPU_FWD_GARP_CFG

Enables CPU forwarding per GARP address.

Per port

CPU_FWD_CCM_CFG

Enables CPU forwarding per CCM/Link trace

address

Per port

CPUQ_CFG and

CPUQ_CFG2

CPU extraction queues for various frame types

None

CPUQ_8021_CFG

CPU extraction queues for BPDU, GARP, and CCM

addresses.

None

VRAP_CFG

VLAN configuration of VRAP filter.

None

VRAP_HDR_DATA

Data match against VRAP header.

None

VRAP_HDR_MASK

Mask used to don’t care bits in the VRAP header.

None

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