VSC7511 datasheet(42/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

3.3.4

SERDES1G Deserializer Configuration

The SERDES1G block includes digital control logic that interacts with the analog modules within the

block and compensates for the frequency offset between the received data and the internal high-speed

reference clock. To gain high jitter performance, the phase regulation is a PI-type regulator, whose

proportional (P) and integrative (I) characteristics can be independently configured. The integrative part

of the phase regulation loop is configured inSERDES1G_DES_CFG.DES_PHS_CTRL. The limits of the

integrator are programmable, allowing different settings for the integrative regulation while guaranteeing

that the proportional part still is stronger than the integrative part. Integrative regulation compensates

frequency modulation from DC up to cut-off frequency. Frequencies above the cut-off frequency are

compensated by the proportional part. The time constant of the integrator is controlled independently of

the proportional regulation by SERDES1G_DES_CFG.DES_BW_HYST. The DES_BW_HYST register

field is programmable in a range from 3 to 7. The lower the configuration setting, the smaller the time-

constant of the integrative regulation. For normal operation, configure DES_BW_HYST to 5.

The cut-off-frequency is calculated to:

fco = 1/(2 × PI × 128 × PLL period × 32 × 2^(DES_BW_HYST + 1 – DES_BW_ANA))

PLL period = 1/(data rate)

The integrative regulator can compensate a static frequency offset within the programmed limits down to

a remaining frequency error of below 4 ppm. In steady state, the integrator toggles between two values

around the exact value, and the proportional part of the phase regulation takes care of the remaining

phase error.

The loop bandwidth for the proportional part of the phase regulation loop is controlled by configuring

SERDES1G_DES_CFG.DES_BW_ANA.

The fastest loop bandwidth setting (lowest configuration value) results in a loop bandwidth that is equal to

the maximum frequency offset compensation capability. For improved jitter performance, use a setting

with sufficient margin to track the expected frequency offset rather than using the maximum frequency

offset. For example, if a 100 ppm offset is expected, use a setting that is four times higher than the offset.

The following table provides the limits for the frequency offset compensation. The values are theoretical

limits for input signals without jitter, because the actual frequency offset compensation capability is

dependent on the toggle rate of the input data and the input jitter. Note that only applicable configuration

values are listed.

In the event of an 180° phase jump of the incoming data signal, the sampling stage of the deserializer

may become stuck. To prevent this situation, the SERDES1G provides a 180° deadlock protection

mechanism (SERDES1G_DES_CFG.DES_MBTR_CTRL). If this mechanism is enabled, a small

frequency offset is applied to the phase regulation loop. The offset is sufficient to move the sampling

point out of the 180° deadlock region, while at the same time, small enough to allow the regulation loop to

compensate when the sample point is within the data eye.

3.3.5

SERDES1G Serializer Configuration

The serializer provides the ability to align the phase of the internal clock and data to a selected source

(SERDES1G_SER_CFG.SER_ENALI). The phase align logic is used when SERDES1G operates in the

facility loopback mode.

Table 15 •

SERDES1G Loop Bandwidth

DES_BW_ANA

Limits

1953 ppm

977 ppm

488 ppm

244 ppm

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