VSC7511 datasheet(44/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

The output buffer supports an idle mode (SERDES1G_SER_CFG.SER_IDLE), which results in an

differential peak-to-peak output amplitude of less than 30 mV.

3.3.8

SERDES1G Clock and Data Recovery (CDR) in 100BASE-FX

To enable clock and data recovery when operating the SERDES1G in 100BASE-FX mode, set the

following registers.

•

SERDES1G_MISC_CFG.DES_100FX_CPMD_ENA = 1

•

SERDES1G_IBJ_CFG.IB_FX100_ENA = 1

•

SERDES1G_DES_CFG.DES_CPMD_SEL = 2

3.3.9

Energy Efficient Ethernet

The SERDES1G block supports Energy Efficient Ethernet as defined in IEEE 802.3az. To enable the low

power modes, SERDES1G_MISC_CFG.TX_LPI_MODE_ENA and

SERDES1G_MISC_CFG.RX_LPI_MODE_ENA must be set. At this point, the attached PCS takes full

control over the high-speed output and input buffer activity.

3.3.10

SERDES1G Data Inversion

The data streams in the transmit and the receive direction can be inverted using

SERDES1G_MISC_CFG.TX_DATA_INV_ENA and SERDES1G_MISC_CFG.RX_DATA_INV_ENA.

Effectively this allows for swapping the P and N lines of the high-speed serial link.

3.4

SERDES6G

The SERDES6G is a high-speed SerDes interface that operates at 100 Mbps (100BASE-FX), 1 Gbps

(SGMII/SerDes), 2.5 Gbps (SGMII), and 5 Gbps (QSGMII). The 100BASE-FX mode is supported by

oversampling.

The following table lists the registers associated with SERDES6G.

For increased performance in specific application environments, SERDES6G supports the following:

•

Baud rate support, configurable from 1 Gbps to 2.5 G, for quarter and half rate modes

•

Programmable loop bandwidth and phase regulation for the deserializer

•

Configurable input buffer feature such as signal detect/loss of signal (LOS) options

•

Configurable output buffer features such as programmable de-emphasis, amplitude drive levels and

slew rate control

•

Synchronous Ethernet support

•

Loopbacks for system test

Table 16 •

SERDES6G Registers

Registers

Description

Replication

SERDES6G_COMMON_CFG

Common configuration

Per SerDes

SERDES6G_DES_CFG

Deserializer configuration

Per SerDes

SERDES6G_IB_CFG

Input buffer configuration

Per SerDes

SERDES6G_IB_CFG1

Input buffer configuration

Per SerDes

SERDES6G_SER_CFG

Serializer configuration

Per SerDes

SERDES6G_OB_CFG

Output buffer configuration

Per SerDes

SERDES6G_OB_CFG1

Output buffer configuration

Per SerDes

SERDES6G_PLL_CFG

PLL configuration

Per SerDes

SERDES6G_MISC_CFG

Miscellaneous configuration

Per SerDes

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