VSC7511 datasheet(33/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

3.2.1.1

Reset

There are a number of resets in the port module. All of the resets can be set and cleared simultaneously.

By default, all blocks are in the reset state. With reference to register CLOCK_CFG, the resets are as

follows:

•

MAC_RX_RST: Reset of the MAC receiver

•

MAC_TX_RST: Reset of the MAC transmitter

•

PORT_RST: Reset of the ingress and egress queues

•

PCS_RX_RST: Reset of the PCS decoder

•

PCS_TX_RST: Reset of the PCS encoder

When changing the MAC configuration, the port must go through a reset cycle. This is done by writing

are cleared. Bits that are not reset bits in CLOCK_CFG must keep their new value for both writes.

For more information about resetting a port, see Port Reset Procedure, page 221.

3.2.1.2

Port Mode Configuration

The MAC provides a number of handles for configuring the port mode. With reference to the

MAC_MODE_CFG, MAC_IFG_CFG, and MAC_ENA_CFG registers, the handles are as follows:

•

Duplex mode (FDX_ENA). Half or full duplex.

•

Data sampling (GIGA_MODE_ENA). Must be 1 in 1 Gbps and 2.5 Gbps and 0 in 10 Mbps and

100 Mbps.

•

Enabling transmission and reception of frames (TX_ENA/RX_ENA). Clearing RX_ENA stops the

reception of frames and further frames are discarded. An ongoing frame reception is interrupted.

Clearing TX_ENA stops the dequeuing of frames from the egress queues, which means that frames

are held back in the egress queues. An ongoing frame transmission is completed.

•

Tx-to-Tx inter-frame gap (TX_IFG)

The link speed is configured using CLOCK_CFG.LINK_SPEED with the following options.

•

Link speed (CLOCK_CFG.LINK_SPEED)

1 Gbps (125 MHz clock)

Ports 8 and 9: 1 Gbps or 2.5 Gbps (125 MHz or 312.5 MHz clock). The actual clock frequency

depends on the SerDes configuration.

100 Mbps (25 MHz clock)

10 Mbps (2.5 MHz clock)

3.2.1.3

Half Duplex

A number of special configuration options are available for half-duplex (HDX) mode:

•

Seed for back-off randomizer. Field MAC_HDX_CFG.SEED seeds the randomizer used by the

backoff algorithm. Use MAC_HDX_CFG.SEED_LOAD to load a new seed value.

DEV::MAC_TAGS_CFG

VLAN tag length configuration

Per port

DEV::MAC_ADV_CHK_CFG

Type length configuration

Per port

DEV::MAC_IFG_CFG

Interframe gap configuration

Per port

DEV::MAC_HDX_CFG

Half-duplex configuration

Per port

SYS::MAC_FC_CFG

Flow control configuration

Per port

DEV::MAC_FC_MAC_LOW_CFG

LSB of SMAC used in pause frames

Per port

DEV::MAC_FC_MAC_HIGH_CFG

MSB of SMAC used in pause frames

Per port

DEV::MAC_STICKY

Sticky bit recordings

Per port

Table 6 •

MAC Configuration Registers (continued)

Description

Replication

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