VSC7511 datasheet(43/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

3.3.6

SERDES1G Input Buffer Configuration

The SERDES1G input buffer supports the following configurable options:

•

100BASE-FX mode support

•

Signal detection, threshold configurable

•

Configurable equalization including corner frequency configuration for the equalization filter

•

DC voltage offset compensation

•

Configurable common mode voltage (CMV) termination

•

Selectable hysteresis, configurable hysteresis levels

When the SerDes interface operates in 100BASE-FX mode, the input buffer of the SERDES1G macro

must also be configured for 100BASE-FX (SERDES1G_IB_CFG.IB_FX100_ENA).

The input buffer provides an option to configure the threshold level of the signal detect circuit to adapt to

different input amplitudes. The signal detect circuit can be configured by

SERDES1G_IB_CFG.IB_ENA_DETLEV and SERDES1G_IB_CFG.IB_DET_LEV.

The SERDES1G block offers options to compensate for channel loss. Degraded signals can be

equalized, and the corner frequency of the equalization filter can be adapted to the channel behavior.

The equalization settings are configured by SERDES1G_IB_CFG.IB_EQ_GAIN and

SERDES1G_IB_CFG.IB_CORNER_FREQ.

The SERDES1G block can compensate for possible DC-offset, which can distort the received input

signal, by enabling SERDES1G_IB_CFG.IB_ENA_OFFSET_COMP during normal reception.

The common-mode voltage (CMV) input termination can be set to either an internal reference voltage or

to VDD_A. To allow external DC-coupling of the input buffer to an output buffer, set the CMV input

termination to the internal reference voltage, with internal DC-coupling disabled.

SERDES1G_IB_CFG.IB_ENA_DC_COUPLING controls internal DC-coupling, and

SERDES1G_IB_CFG.IB_ENA_CMV_TERM controls CMV input termination. The following modes are

defined by CMV input termination and DC-coupling.

•

SGMII compliant mode with external AC coupling (IB_ENA_DC_COUPLING = 0,

IB_ENA_CMV_TERM = 1)

•

Microsemi-mode with external DC-coupling to another Versatile output buffer, which can operate

DC-coupled to the input buffer (IB_ENA_DC_COUPLING = 0, IB_ENA_CMV_TERM = 0)

•

100BASE-FX low frequency mode (IB_ENA_DC_COUPLING = 1, IB_ENA_CMV_TERM = 1)

The SERDES1G macro supports input hysteresis, which is required for some standards (SGMII). The

hysteresis function is enabled by SERDES1G_IB_CFG.IB_ENA_HYST, and hysteresis levels are defined

by SERDES1G_IB_CFG.IB_HYST_LEV.

Note: Hysteresis and DC offset compensation cannot be enabled at the same time. For more information, see

IB_ENA_OFFSET_COMP in the SERDES1G_IB_CFG register.

3.3.7

SERDES1G Output Buffer Configuration

The SERDEDS1G output buffer supports the following configurable options.

•

Configurable amplitude settings

•

Configurable slew rate control

•

3 dB de-emphasis selectable

•

Idle mode

The output amplitude of the output buffer is controlled by SERDES1G_OB_CFG.OB_AMP_CTRL. It can

be adjusted in 50 mV steps from 0.4 V to 1.1 V peak-to-peak differential. The output amplitude also

depends on the output buffer’s supply voltage. For more information about dependencies between the

maximum achievable output amplitude and the output buffer’s supply voltage, refer to the electrical

section for the dependencies between the maximum achievable output amplitude and the output buffer’s

supply voltage.

Adjust the slew rate adjustment using SERDES1G_OB_CFG.OB_SLP.

The output buffer supports a fixed 3 dB de-emphasis (SERDES1G_SER_CFG.SER_DEEMPH).

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