VSC7511 datasheet(50/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

•

The SerDes macro address is a mask with one bit per macro so that one or more macros can be

programmed at the same time.

•

The MCB_SERDES6G_ADDR_CFG.SERDES6G_WR_ONE_SHOT are automatically cleared

when the writing is done.

The configuration and status information in the SERDES6G macros can be read as follows:

•

Transfer the configuration and status from one or more SerDes macros to the configuration registers

by writing the address of the macro (MCB_SERDES6G_ADDR_CFG.SERDES6G_ADDR) and

initiating the read access (MCB_SERDES6G_ADDR_CFG.SERDES6G_RD_ONE_SHOT).

•

The SerDes macro address is a mask with one bit per macro so that configuration and status

information from one or more macros can be read at the same time. When reading from more than

one macro, the results from each macro are OR’ed together.

•

The MCB_SERDES6G_ADDR_CFG.SERDES6G_RD_ONE_SHOT are automatically cleared when

the reading is done.

The SERDES1G macros are programmed similarly to the SERDES6G macros, except that

MCB_SERDES1G_ADDR_CFG must be used for register access. For more information about

configuration options, see SERDES1G, page 25.

3.5

Copper Transceivers

This section describes the high-level functionality and operation of four built-in copper transceivers. The

integration is kept as close to multichip PHY and switch designs as possible. This allows a fast path for

software already running in a similar distributed design while still benefiting from the cost savings

provided by the integration.

3.5.1

The registers of the integrated transceivers are not placed in the memory map of the switch, but are

attached instead to the built-in MII management controller 0 of the device. As a result, PHY registers are

accessed indirectly through the switch registers. For more information, see MII Management Controller,

page 201.

In addition to providing the IEEE 802.3 specified 16 MII Standard Set registers, the PHYs contain an

extended set of registers that provide additional functionality. The devices support the following types of

registers:

•

IEEE Clause 22 device registers with addresses from 0 to 31

•

Two pages of extended registers with addresses from 16E1 through 30E1 and 16E2 through 30E2

•

General-purpose registers with addresses from 0G to 30G

•

IEEE Clause 45 device registers accessible through the Clause 22 registers 13 and 14 to support

IEEE 802.3az Energy Efficient Ethernet registers

The memory mapping is controlled through PHY_MEMORY_PAGE_ACCESS::PAGE_ACCESS_CFG.

The following illustration shows the relationship between the device registers and their address spaces.

Figure 9 •

IEEE 802.3

Standard

Registers

Main Registers

0x0000

Extended

Registers 1

0x0001

16E1

17E1

18E1

19E1

30E1

Extended

Registers 2

0x0002

16E2

17E2

18E2

19E2

30E2

Extended

Registers 3

0x0003

16E3

17E3

18E3

19E3

30E3

General Purpose

Registers

0x0010

15G

16G

17G

18G

19G

30G

Clause 45

Registers

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