VSC7511 datasheet(45/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

3.4.1

SERDES6G Basic Configuration

The SERDES6G is enabled in SERDES6G_COMMON_CFG.ENA_LANE. By default, the SERDES6G is

held reset and must be released from reset before the interface is active. This is done through

SERDES6G_COMMON_CFG.SYS_RST and SERDES6G_MISC_CFG.LANE_RST.

3.4.1.1

SERDES6G PLL Frequency Configuration

To operate the SERDES6G block at the correct frequency, configure the internal macro as follows. PLL

calibration is enabled through SERDES6G_PLL_CFG.PLL_FSM_ENA.

•

Configure SERDES6G_PLL_CFG.PLL_FSM_CTRL_DATA in accordance with data rates listed in

the following tables.

•

Set SYS_RST = 0 (active) and PLL_FSM_ENA = 0 (inactive).

•

Set SYS_RST = 1 (deactive) and PLL_FSM_ENA = 1 (active).

3.4.1.2

SERDES6G Frequency Configuration

The following table lists the range of data rates that are supported by the SERDES6G block.

3.4.2

SERDES6G Loopback Modes

The SERDES6G interface supports two different loopback modes for testing and debugging data paths:

equipment loopback and facility loopback.

3.4.2.1

Equipment Loopback (SERDES6G_COMMON_CFG.ENA_ELOOP)

Data is looped back from serializer output to the deserializer input, and the receive clock is recovered.

The equipment loopback includes all transmit and receive functions, except for the input and output

buffers. The Tx data can still be observed on the output.

3.4.2.2

Facility Loopback (SERDES6G_COMMON_CFG.ENA_FLOOP)

The clock and parallel data output from deserializer are looped back to the serializer interface. Incoming

serial data passes through the input buffer, the CDR, the deserializer, back to the serializer, and finally

out through the output buffer.

Only one of the loopbacks can be enabled at the same time.

The following illustration shows the loopback paths for the SERDESG6.

Table 17 •

PLL Configuration

Mode

SERDES6G_PLL_CFG.PLL_FSM_CTRL_DATA

SGMII/SerDes, 1 Gbps data

SGMII, 2.5 Gbps data

Table 18 •

SERDES6G Frequency Configuration Registers

Configuration

SGMII/SerDes

1Gbps

SGMII

2.5 Gbps

SERDES6G_PLL_CFG.PLL_ROT_FRQ

SERDES6G_PLL_CFG.PLL_ROT_DIR

SERDES6G_PLL_CFG.PLL_ENA_ROT

SERDES6G_COMMON_CFG.QRATE

SERDES6G_COMMON_CFG.HRATE

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