VSC7511 datasheet(39/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

PCS1G_TSTPAT_MODE_STATUS register holds information about error and lock conditions while

running the jitter test patterns.

3.2.2.6

Low Power Idle

The following table lists the registers associated with low power idle (LPI).

The PCS supports Energy Efficient Ethernet (EEE) as defined by IEEE 802.3az. The PCS converts Low

Power Idle (LPI) encoding between the MAC and the serial interface transparently. In addition, the PCS

provides control signals allowing to stop data transmission in the SerDes macro. During low power idles

the serial transmitter in the SerDes macro can be powered down, only interrupted periodically while

transmitting refresh information, which allows the receiver to notice that the link is still up but in power

down mode.

For more information about powering down the serial transmitter in the SerDes macros, see SERDES1G,

page 25 or SERDES6G, page 29.

It is not necessary to enable the PCS for EEE, because it is controlled indirectly by the shared queue

system. It is possible, however, to manually force the PCS into the low power idle mode through

PCS1G_LPI_CFG.TX_ASSERT_LPIDLE. During LPI mode, the PCS constantly encodes low power idle

with periodical refreshes. For more information about EEE, see Energy Efficient Ethernet, page 127.

The current low power idle state can be observed through PCS1G_LPI_STATUS for both receiver and

transmitter:

•

RX_LPI_MODE: Set if the receiver is in low power idle mode.

•

RX_QUIET: Set if the receiver is in the Quiet state of the low power idle mode. If cleared while

RX_LPI_MODE is set, the receiver is in the refresh state of the low power idle mode.

The same is observable for the transmitter through TX_LPI_MODE and TX_QUIET.

If an LPI symbol is received, the RX_LPI_EVENT_STICKY bit is set, and if an LPI symbol is transmitted,

the TX_LPI_EVENT_STICKY bit is set. These events are sticky.

The PCS1G_LPI_WAKE_ERROR_CNT wake-up error counter increments when the receiver detects a

signal and the PCS is not synchronized. This can happen when the transmitter fails to observe the wake-

up time or if the receiver is not able to synchronize in time.

3.2.2.7

100BASE-FX

The following table lists the registers associated with 100BASE-FX configuration.

The PCS supports a 100BASE-FX mode in addition to the SGMII and 1000BASE-X SerDes modes. The

100BASE-FX mode uses 4-bit/5-bit coding as specified in IEEE 802.3 Clause 24 for fiber connections.

The 100BASE-FX mode is enabled through PCS_FX100_CFG.PCS_ENA, which masks out all PCS1G

related registers.

The following options are available:

Table 12 •

Low Power Idle Registers

Registers

Description

Replication

PCS1G_LPI_CFG

Configuration of the PCS low power idle process

Per PSC

PCS1G_LPI_WAKE_ERROR_CNT

Error counter

Per PCS

PCS1G_LPI_STATUS

Low Power Idle status

Per PCS

Table 13 •

100BASE-FX Registers

Registers

Description

Replication

PCS_FX100_CFG

Configuration of the PCS 100BASE-FX mode

Per PSC

PCS_FX100_STATUS

Status of the PCS 100BASE-FX mode

Per PCS

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