AD9929BBCZ datasheet(30/64 Pages) AD

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AD9929

Rev. A | Page 30 of 64

CLPOB

12-BIT

GRAY COUNTER

+ SET-UP

PROGRAMMABLE CLOCK POSITIONS

1. CLPTOG1 (SYS_REG (15))

2. CLPTOG2 (SYS_REG (15 AND 16))

Figure 25. Location of CLPOB using CLPTOG1 and CLPTOG2 Registers.

CLPOB

CLPMASK

(INTERNAL)

PROGRAMMING POSITIONS

1. SCP0 = 0 (FIXED), CLPEN0 = 1

2. SCP1 = 3, CLPEN1 = 0

3. SCP2 = 4, CLPEN2 = 1

4. SCP3 = 5, CLPEN3 = 0

5. SCP4 = 1, CLPEN4 = 1

NOTES

1. THE INTERNAL CLPMASK SIGNAL EXTENDS ONE EXTRA HD CYCLE FROM WHEN THE CLPMASK PERIOD CHANGES FROM LOW TO HIGH.

AS A RESULT, ONE ADDITIONAL CLPOB PULSE IS MASKED AS SHOWN AT POSITIONS A AND B.

Figure 26. CLPOB Outputs with CLPMODE = 0

CONTROLLING CLPOB CLAMP PULSE OUTPUTS

The registers in Table 19 are used for programming the CLPOB

pulse. The CLPOB pulse is disabled in all CCD regions by

setting CLPCNT = 0. The CLPTOGx (x = 0, 1) are used to set

the CLPOB toggle positions. The CLPENx (x = 0, 1, 2, 3, and 4)

are used to enable or disable the CLPOB pulse separately in

each CCD region when CLPMODE = 0. The CLPEN registers

have no effect if CLPMODE = 1. In this case, the CLPOB pulse

is asserted in all CCD regions, regardless of the value set in the

CLPENx registers.

Figure 26 shows an example of the CLPOB pulse being disabled

in CCD Regions 1 and 3 by setting CLPEN1 = 1 and

CLPEN3 =1. Note that the CLPOB pulse remains disabled in

the first line of the following CCD region.

Table 20. SCP and CLPEN

SCP[4:1]1

CLPEN[4:0]

SCP0

CLPEN0

SCP1

CLPEN1

SCP2

CLPEN2

SCP3

CLPEN3

SCP4

CLPEN4

1 SCP0 is not a programmable register and therefore not listed in the register

map tables. SCP0 is a fixed sequence and always starts at the falling edge of

VD. Although this register is not programmable, the CLPEN0 register is still

used to set whether the CLPOB pulse is enabled or disabled for this SCP0

region.

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