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AD9929BBCZ датащи(PDF) 29 Page - Analog Devices |
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AD9929BBCZ датащи(HTML) 29 Page - Analog Devices |
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29 / 64 page ![]() AD9929 Rev. A | Page 29 of 64 HORIZONTAL CLAMPING AND BLANKING The AD9929’s horizontal clamping and blanking pulses are programmable to suit a variety of applications. As with the vertical timing generation, individual sequences are defined for each signal, which are then organized into multiple regions during image readout. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout, in order to accommodate different image transfer timing and high speed line shifts. CONTROLLING CLPOB CLAMP PULSE TIMING The AFE horizontal CLPOB pulse is generated based on the 12-bit gray code counter. Once the length of the 12-bit gray code counter is set using the HDLEN register (Sys_Reg(12)), the CLPTOG1 and CLPTOG2 registers (Sys_Reg(15 and 16)) can be used to place the CLPOB pulse location, as shown in Figure 25. Table 19 lists all CLPOB registers that are used to configure and control the placement and output of the CLPOB pulse. The length of the last HD line is set using the HDLASTLEN register (Sys_Reg(1)). Figure 23 shows how no CLPOB pulse is asserted when the last HD length set by HDLASTLEN is shorter than the regular HD length set by HDLEN. Figure 24 shows how no CLPOB pulse is applied when the last HD length set by HDLASTLEN is longer than the regular HD length. Note that the CLPOB pulse is applied in the last line only when HDLASTLEN = HDLEN. HD CLPOB LAST LINE Figure 23. Last HD Shorter than Regular HD HD CLPOB LAST LINE Figure 24. Last HD Longer than Regular HD Table 19. CLPOB Registers Register Name Bit Width Register Type Counter Reference Range Description CLPOB_CONT 1 Control (0x01) – CLPOB Control (0=CLPOB off, 1 =CLPOB On) CLPOB_MODE 1 Control (0x01) – CLPOB CCD Region Control (0 = Enable CLPENx Register Settings, 1 = Disable CLPENx Register Settings) CLPTOG1 12 Sys_Reg (15) HD 0 to 4095 pixel locations CLPOB Toggle Position 1 (Gray Code Number) CLPTOG2 12 Sys_Reg (15 and 16) HD 0 to 4095 pixel locations CLPOB Toggle Position 2 (Gray Code Number) CLPEN0 1 Mode_Reg (2) – CLPOB Control for CCD Region 0 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPEN1 1 Mode_Reg (2) – CLPOB Control for CCD Region 1 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPEN2 1 Mode_Reg (2) – CLPOB Control for CCD Region 2 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPEN3 1 Mode_Reg (2) – CLPOB Control for CCD Region 3 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPEN4 1 Mode_Reg (2) – CLPOB Control for CCD Region 4 (0 = CLPOB Disabled, 1 = CLPOB Enabled) |
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