AD9929BBCZ datasheet(23/64 Pages) AD

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AD9929

Rev. A | Page 23 of 64

Variable Gain Amplifier

The VGA provides a gain range of 6 dB to 40 dB, programmable

with 10-bit resolution through the serial digital interface. The

minimum gain of 6 dB is needed to match a 1 V input signal

with the ADC full-scale range of 2 V.

The VGA gain curve follows a “linear-in-dB” characteristic. The

exact VGA gain can be calculated for any gain register value by

using the equation

Gain = (0.035 × Code) + 5.2

where the code range is 0 to 1023. Figure 14 shows a typical

AD9929 VGA gain curve.

VGA GAIN REGISTER CODE

127

255

383

511

639

767

895

1023

Figure 14. VGA Gain Curve

Optical Black Clamp

The optical black clamp loop is used to remove residual offsets

in the signal chain and to track low frequency variations in the

CCD’s black level. During the optical black (shielded) pixel

interval on each line, the ADC output is compared with a fixed

black level reference selected by the user in the clamp level

grammed with 8-bit resolution. The resulting error signal is

filtered to reduce noise, and the correction value is applied to

the ADC input through a D/A converter. Normally, the optical

black clamp loop is turned on once per horizontal line, but this

loop can be updated more slowly to suit a particular application.

The optical black clamp is controlled by the CLPOB signal,

which is fully programmable (see Horizontal Clamping and

Blanking section). System timing examples are shown in the

Horizontal and Vertical Synchronous Timing section. The

CLPOB pulse should be placed during the CCDs optical black

pixels. It is recommended that the CLPOB pulse duration be at

least 20 pixels wide. Shorter pulse widths may be used, but the

ability to track low frequency variations in the black level is

reduced.

A/D Converter

The AD9929 uses high-performance 12-bit ADC architecture,

optimized for high speed and low power. Differential Non-

linearity (DNL) performance is typically better than 0.5 LSB.

The ADC uses a 2 V input range. Better noise performance

results from using a larger ADC full-scale range.

PRECISION TIMING, HIGH SPEED TIMING

GENERATION

The AD9929 generates flexible, high speed timing signals using

the precision timing core. This core is the foundation for gener-

ating the timing used for both the CCD and the AFE: the reset

gate RG, horizontal drivers H1 to H2, and the CDS sample

clocks. A unique architecture makes it routine for the system

designer to optimize image quality by providing precise control

over the horizontal CCD readout and the AFE correlated

double sampling.

Timing Resolution

The precision timing core uses the master clock input (CLI) as a

reference. This clock should be the same as the CCD pixel clock

frequency. Figure 15 illustrates how the internal timing core

divides the master clock period into 48 steps or edge positions.

Using a 36 MHz CLI frequency, the edge resolution of the

precision timing core is 0.58 ns. A 72 MHz CLI frequency can

be applied to the AD9929, where the AD9929 will internally

divide the CLI frequency by two. Division by 1/3 and 1/4 are

also provided. CLI frequency division is controlled by using

CLKDIV (Address 0x05) register.

High Speed Clock Programmability

Figure 17 shows how the high speed clocks RG, H1 to H2, SHP,

and SHD are generated. The RG pulse has a fixed rising edge

and a programmable falling edge. The horizontal clock H1 has a

programmable rising and a fixed falling edge occurring at

H1POSLOC + 24 steps. The H2 clock is always the inverse of

H1. Table 14 summarizes the high speed timing registers and

the parameters for the high speed clocks. Each register is 6 bits

wide with the 2 MSB bits used to select the quadrant region, as

outlined in Table 16. Figure 17 shows the range and default

locations of the high speed clock signals.

H DRIVER AND RG OUTPUTS

In addition to the programmable timing positions, the AD9929

features on-chip output drivers for the RG and H1 to H2 out-

puts. These drivers are powerful enough to directly drive the

CCD inputs. The H-driver current can be adjusted for optimum

rise/fall time into a particular load by using the H1DRV and

H2DRV registers (Address 0x04). The RG drive current is

adjustable using the RGDRV register (Address 0x04). The

H1DRV and H2DRV register is adjustable in 4.3 mA incre-

ments. The RGDRV register is adjustable in 2.15 mA incre-

ments. All DRV registers have settings of 0 equal to OFF or

three-state, and a maximum setting of 7.

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