AD9929BBCZ datasheet(40/64 Pages) AD

40 / 64 page

AD9929

Rev. A | Page 40 of 64

SPECIAL VERTICAL TIMING (SPATS)

The AD9929 provides additional special vertical timing gen-

eration (SPATs), which is applied in the same line as the VSG

pulse. The SPAT timing allows for an additional vertical output

pulse in the VSG line. The additional vertical output pulse can

be applied to either XV1, XV2, XV3 or XV4, according to the

value of the SPATLOGIC register. Table 26 lists the registers

used to generate the SPATs, and Table 27 describes the

SPATLOGIC settings and operation.

Figure 39 and Figure 40 show AND and OR SPAT pulse

examples using four SPAT toggle positions. As shown in these

figures, the internal SPAT timing for the AND case initially

starts high and then goes low at the first XVxSPAT_TOG1

position. In the OR case, the internal SPAT timing initially starts

low and then toggles high at the first XVxSPAT_TOG1 position.

This provides the ability to output the second vertical pulse

when the internal XVx pulse is in both high and low states. Note

that although Figure 39 and Figure 40 show four SPAT toggle

positions, two SPAT toggle positions can be applied by setting

XVxSPAT_TOG3 = XVxSPAT_TOG4 = 0x1FFF.

Table 26. HD and VD Registers

Bit

Width

Reference

Counter

Range (Pixels)

Description

SPAT_EN

Control (Address 0x01)

–

SPAT Enable Control

(0 = SPAT Disabled, 1 = SPAT Enabled)

SPATLOGIC

Control (Address 0x0A)

–

SPAT Logic Setting

XV1SPAT_TOG1

Control (Address 0x17)

0–8192

XV1SPAT Toggle Position #1

(Mode_A Active)

XV1SPAT_TOG2

Control (Address 0x18)

0–8192

XV1SPAT Toggle Position #2

(Mode_A Active)

XV1SPAT_TOG3

Mode_A_Reg(5)

0–8192

XV1SPAT Toggle Position #3

(Mode_A Active)

XV1SPAT_TOG4

Mode_A_Reg(5)

0–8192

XV1SPAT Toggle Position #4

(Mode_A Active)

XV2SPAT_TOG1

Control (Address 0x19)

0–8192

XV2SPAT Toggle Position #1

(Mode_A Active)

XV2SPAT_TOG2

Control (Address 0x1A)

0–8192

XV2SPAT Toggle Position #2

(Mode_A Active)

XV2SPAT_TOG3

Mode_A_Reg(5)

0–8192

XV2SPAT Toggle Position #3

(Mode_A Active)

XV2SPAT_TOG4

Mode_A_Reg(5)

0–8192

XV2SPAT Toggle Position #4

(Mode_A Active)

XV3SPAT_TOG1

Control (Address 0x1B)

0–8192

XV3SPAT Toggle Position #1

(Mode_A Active)

XV3SPAT_TOG2

Control (Address 0x1C)

0–8192

XV3SPAT Toggle Position #2

(Mode_A Active)

XV3SPAT_TOG3

Mode_A_Reg(5)

0–8192

XV3SPAT Toggle Position #3

(Mode_A Active)

XV3SPAT_TOG4

Mode_A_Reg(5)

0–8192

XV3SPAT Toggle Position #4

(Mode_A Active)

XV4SPAT_TOG1

Control (Address 0x1D)

0–8192

XV4SPAT Toggle Position #1

(Mode_A Active)

XV4SPAT_TOG2

Control (Address 0x1E)

0–8192

XV4SPAT Toggle Position #2

(Mode_A Active)

XV4SPAT_TOG3

Mode_A_Reg(5)

0–8192

XV4SPAT Toggle Position #3

(Mode_A Active)

XV4SPAT_TOG4

Mode_A_Reg(5)

0–8192

XV4SPAT Toggle Position #4

(Mode_A Active)

XV1SPAT_TOG1

Control (Address 0x1F)

0–8192

XV1SPAT Toggle Position #1

(Mode_B Active)

XV1SPAT_TOG2

Control (Address 0x20)

0–8192

XV1SPAT Toggle Position #2

(Mode_B Active)

XV1SPAT_TOG3

Mode_B_Reg(5)

0–8192

XV1SPAT Toggle Position #3

(Mode_B Active)

XV1SPAT_TOG4

Mode_B_Reg(5)

0–8192

XV1SPAT Toggle Position #4

(Mode_B Active)

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