AD9929BBCZ datasheet(48/64 Pages) AD

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AD9929

Rev. A | Page 48 of 64

VSG TIMING

The VSG Timing is controlled using the registers in Table 35.

Two unique preprogrammed VSG pulses can be configured

using the XVSGTOG_x (x = 0, 1) registers. As shown in

Figure 55, the period of the VSG pulse is set by programming

the XVSGLEN_x registers. The XVSGSELx (x = 1, 2) can then

be used to select the XVSGTOG_0 or XVSGTOG_1 pulse.

Figure 55 also shows an example of the XVSG pulse being

output in the fourth line by setting the XVSGACTLINE = 3.

The XVSG pulses references the 13-bit fixed ST counter, which

starts counting from the line set in the XVSGACTLINE register.

The 13-bit counter allows for overlapping of the XVSG pulse

into the next line if needed.

Figure 53 describes the XVSG1 and XVSG2 MUX operation

using the XVSGSELx registers.

XVSGTOG_0

XVSGTOG_1

XVSGSEL1

XVSG1

XVSGTOG_0

XVSGTOG_1

XVSGSEL2

XVSG2

(APPLIED TO XV1)

(APPLIED TO XV3)

Figure 53. XVSGSELx Registers

XSUBCK

9-BIT

OL-COUNTER

Figure 54. Electronic Shutter Timing Example with XSUBCKMODE_HP = 1 and XSUBCKNUM_HP = 3.

Table 35. VSG Registers

Name

Bit

Width

Reference

Counter

Range

Description

XVSGMASK

Control (Address 0x0A)

–

VSG Mask Control

(00 = XVSG1 Masked, XVSG2 Masked)

(02 = XVSG1 Not Masked, XVSG2 Masked)

(08 = XVSG1 Masked, XVSG2 Not Masked)

(0A= XVSG1 Not Masked, XVSG2 Not Masked)

XVSG_EN

Control (Address 0x0B)

–

High/Low

XVSG Output Enable Control (0 = Disable

XVSG Outputs, 1 = Enable XVSG Outputs)

XVSGTOG_0

Sys_Reg(13)

0–8191 Pixels

XVSGTOG_0 Toggle Position

XVSGTOG_1

Sys_Reg(13)

0–8191 Pixels

XVSG TOG_1 Toggle Position

XVSGLEN_0

Sys_Reg(14)

0–255 Pixels

XVSGTOG_0 Pulse Width

XVSGLEN_1

Control (Address 0x0F)

0–255 Pixels

XVSGTOG_1 Pulse Width

XVSGSEL1

Mode_Reg(1)

–

High/Low

XVSG1 Selector

(0 = XVSGTOG_0 Applied on XVSG1,

1 = XVSGTOG_1 Applied on XVSG1)

XVSGSEL2

Mode_Reg(1)

–

High/Low

XVSG2 Selector

(0 = XVSGTOG_0 Applied on XVSG2,

1 = XVSGTOG_1 Applied on XVSG2 )

XVSGACTLINE

Mode_Reg(1)

0–128 Lines

VSG Active Line

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