AD9929BBCZ datasheet(28/64 Pages) AD

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AD9929

Rev. A | Page 28 of 64

HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING

The HD and VD output pulses are programmable using the

registers listed in Table 18. The HD output is asserted low at the

start of the horizontal line shift. The VD output is asserted low

at the start of each line. As shown in Figure 22, the 11-bit VD

counter is used to count the number of lines set by the VDLEN

pixels in each line set by the HDLEN register. For example, if

the CCD array size is 2000 lines by 2100 pixels per line,

VDLEN = 2000 and HDLEN = 0xC28. The HDLEN register

sets HL as a reference for the rising edge of the HD pulse.

SPECIAL NOTE ABOUT THE HDLEN REGISTER

The 12-bit HD counter value must be programmed using a gray

code number. There is also a 4-clock cycle, set up period that

must be considered when determining the HDLEN register

value, as shown in Figure 22. As a result of the 4-clock cycle,

setup period, the value of HDLEN is always equal to the actual

number of pixels per line minus 4. For example, if there are

2100 pixels per line, HDLEN equals (2100 – 4) = 2096. The gray

code value of 2096 is 0xC28, which is what would be program-

med in the HDLEN register.

Table 18. HD and VD Registers

Bit

Width

Reference

Counter

Range

Description

HDLEN1

Sys_Reg(12)

–

0–4095 Pixels

12-Bit Gray Code Counter Value

HLEN

Sys_Reg(12)

–

0–1023 Pixels

10-Bit HL-Counter Value

HDRISE

Sys_Reg(16)

0–1023 Pixels

HD Rise Position

HDLASTLEN1

Mode_Reg(1)

0–4095 Pixels

HD Last Line Length

VDLEN

Mode_Reg(1)

–

0–2047 Lines

VD Counter Value

VDRISE

Sys_Reg(16)

0–15 Lines

VD Rise Position

1 Register value must be a gray code number (see Gray Code Registers section).

HDLASTLEN

VDLEN

000

001

002

11-BIT

VD COUNTER

12-BIT

GRAY COUNTER

+ SET- UP

HDLEN

10-BIT

HL COUNTER

NOTES

1. THE SET-UP DELAY IS 4 CLI CYCLES. THE ACTUAL LENGTH OF ONE LINE IS 4 MORE CYCLES

THAN VALUE SET IN HDLEN AND HDLASTLEN DUE TO SET-UP DELAY.

2. VDRISE REFERENCES THE 11-BIT VD-COUNTER.

3. HDRISE REFERENCES THE 10-BIT HL-CONTER.

PROGRAMMABLE CLOCK POSITIONS

1. HDRISE (SYS_REG(16))

2. VDRISE (SYS_REG(16))

N _

< 2048

HLEN

LINE LENGTH =

HDLEN + 4

Figure 22. VD and HD Horizontal Timing

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