AD9929BBCZ datasheet(20/64 Pages) AD

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AD9929

Rev. A | Page 20 of 64

SERIAL INTERFACE TIMING

All of the internal registers of the AD9929 are accessed through

a 3-wire serial interface. The 3-wire interface consists of a clock

(SCK), serial load (SL), and serial data (SDATA).

The AD9929 has three different register types that are confi-

gured by the 3-wire serial interface. As described in Table 13,

the three register types are control registers, system registers,

and mode registers.

Table 13. Types of Serial Interface Registers

Address

Number of Registers

Control

0x00 to

0xD6

24-Bit Registers at Each Address. Not All

Addresses Are Used. See Table 8.

System

0x14

Seventeen 32-Bit System Registers at

Address 0x14. See Table 9.

Mode_A

0x15

Eight 32-bit Mode_A Registers at Address

0x15. See Table 10.

Mode_B

0x16

Eight 32-Bit Mode_B Registers at Address

0x16. See Table 11.

Registers

Control Register Serial Interface

The control register 3-wire interface timing requirements are

shown in Figure 10. Control data must be written into the

device one address at a time due to the noncontiguous address

spacing for the control registers. This requires writing 8 bits of

address data followed by 24 bits of configuration data between

each active low period of SL for each address. The SL signal

must be kept high for at least one full SCK cycle between

successive writes to control registers.

System Register Serial Interface

There are seventeen 32-bit system registers that are accessed

sequentially at Address 0x14, beginning with Sys_Reg [0]. When

writing to the system registers, SDATA contains the 8-bit

Address 0x14, followed by Number Writes N [23:0], followed by

the Sys_Reg [31:0] data, as shown in Figure 5. The system

The value of the Number Writes N [23:0] word determines one

of two options when writing to the system registers. If Number

Writes N[23:0] = 0x000000, the device enters a mode where it

expects all 17 Sys_Reg [31:0] data-words to be clocked in before

SL is asserted high. If the Number Writes N [23:0] is decoded as

some number N other than 0x000000, then the device expects

N number of registers to be programmed, where N equals the

value of Number Writes N [23:0]. For example: if Number

Writes N[23:0] = 0x000004, the device would expect data to be

provided for Sys_Reg [3:0]. In all cases, the system registers are

written beginning with Sys_Reg [0], regardless of the value of

Number Writes N [23:0]. Note that SL can be brought high or

low during access to system registers, as shown in Figure 11.

Mode_A and Mode_B Register Serial Interface

There are eight 32-bit Mode_A and eight 32-bit Mode_B

registers that get accessed sequentially at Address 0x15 and

Address 0x16, respectively. Mode_A and Mode_B registers are

written to in exactly the same way as the system registers, as

explained previously. The mode registers are listed in Table 10

and Table 11.

To change operation between Mode_A and Mode_B, set the

1-bit mode register (Address 0x0A). The desired Mode_A

(Address 0x15) or Mode_B (Address 0x16) data must be

programmed into the Mode_A or Mode_B registers before

changing the mode bit.

SDATA

SCK

D22

D21

tDS

tDH

tLS

tLH

NOTES

1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.

2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.

3. THIS TIMING PATTERN MUST BE WRITTEN FOR EACH REGISTER WRITE WITH SL REMAINING HIGH FOR AT

LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SL LOW AGAIN FOR THE NEXT REGISTER WRITE.

D23

....

Figure 10. 3-Wire Serial Interface Timing for Control Registers

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