AD9929BBCZ datasheet(55/64 Pages) AD

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AD9929

Rev. A | Page 55 of 64

INITIAL START-UP SEQUENCE

Recommended Start-Up Sequence for Master Mode

When the AD9929 is powered up, the following sequence is

recommended (refer to Figure 66 for each step).

Turn on power supplies as described in the Power Supply

Sequencing section.

Apply the CLI master clock input.

CLI is output on DCLK2 Pin 16 at this time.

Reset the internal AD9929 registers. Write a 0x000000 to

the SW_RESET register (Address 0x00). This sets all

internal register values to their default values. (This step is

optional because there is an internal power-on reset circuit

that is applied at power-up.)

Program DIGSTBY and AFESTBY registers (Address 0x05)

= 1 and all other necessary control registers.

Program system registers (Address 0x20).

Program Mode_A registers (Address 0x21).

Program Mode_B registers (Address 0x22).

Program OUTCONT_REG register (Address 0x05) = 1.

(The internal OUTCONT signal is asserted high at this

time. This enables the digital outputs.)

Program control register MODE (Address 0x0A) = 0. This

selects Mode_A operation. (This step is optional because

the AD9929 defaults to Mode_A at power-up.)

10. Program control register MODE (Address 0x0A) = 1. This

selects Mode_B operation. Note: Complete this write at

least 4 CLI cycles before the start of the next field.

AD9929

POWER-UP

SEQUENCE

SERIAL

WRITES

(OUTPUT)

1 H

ODD FIELD

EVEN FIELD

DIGITAL

(OUTPUTS)

H2, RG, MSHUT, STROBE

H1, VSUB, FD

(OUTPUT)

1 V

OUTCONT1

(INTERNAL SIGNAL)

DCLK1

(OUTPUT)

NOTES

1OUTCONT IS AN INTERNAL SIGNAL THAT IS CONTROLLED USING REGISTER OUTCONT_REG (ADDRESS 0x05).

2DCLK2 WILL BE OUTPUT ON THE FD/DCLK2 PIN 16 PROVIDING REGISTER DCLK2SEL (ADDRESS 0xD5) = 1.

THE DCLK2SEL REGISTER DEFAULTS TO 1 AT POWER-UP.

3IT TAKES 11 CLI CLOCKS FROM WHEN OCONT GOES HIGH UNTIL VD, HD, AND DIGITAL OUTPUT DATA IS VALID.

4THERE IS A 500

µS SETTLING TIME FROM WHEN THE DIGSTBY REGISTER IS SET TO WHEN THE DCLK1 IS STABLE.

ODD FIELD

tSETTLING4

CLI

(INPUT)

DCLK22

(OUTPUT)

tDELAY3

tPWR

Figure 66. Recommended Start-Up Sequence and Synchronization, Master Mode

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