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AD9929BBCZ датащи(PDF) 3 Page - Analog Devices

номер детали AD9929BBCZ
подробное описание детали  CCD Signal Processor with Precision Timing Generator
PDF  64 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9929BBCZ датащи(HTML) 3 Page - Analog Devices

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AD9929
Rev. A | Page 3 of 64
SPECIFICATIONS
Table 1.
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
−25
+85
°C
Storage
−65
+150
°C
POWER SUPPLY VOLTAGE
AVDD (AFE Analog Supply)
2.7
3.0
3.6
V
TCVDD (Timing Core Analog Supply)
2.7
3.0
3.6
V
RGVDD (RG Driver)
2.7
3.0
3.6
V
HVDD (H1 to H2 Drivers)
2.7
3.0
3.6
V
DRVDD (Data Output Drivers)
2.7
3.0
3.6
V
DVDD (Digital)
2.7
3.0
3.6
V
VERTICAL DRIVER SUPPLY VOLTAGE
VDD (Vertical Driver Input Logic Supply)
2.7
3.0
3.6
V
VH1, VH2 (Vertical Driver High Supply)
11.5
15.0
16.0
V
VM1, VM2 (Vertical Driver Mid Supply)
−1.0
0.0
1.0
V
VL (Vertical Driver Low Supply for 3 Level and 2 Level)
−9.0
−7.5
−5.0
V
AFETG POWER DISSIPATION
36 MHz, Typ Supply Levels, 100 pF H1 to H2 Loading
180
mW
Power from HVDD Only1
36
mW
Power-down Mode (AFE and Digital in Standby Operation)
1
mW
VERTICAL DRIVER POWER DISSIPATION2 (6000 pF V1 to V4 Loading, 1000 pF SUBCK Loading)
Power from VDD
<1.0
mW
Power from VH1
23.0
mW
Power from VH2
15.0
mW
Power from VL
42.0
mW
MAXIMUM CLOCK RATE (CLI) AD9929
36
MHz
1 The total power dissipated by the HVDD supply may be approximated by using the equation:
Total HVDD Power = [CLOAD × HVDD × Pixel Frequency] × HVDD × Number of H-Outputs Used.
Actual HVDD power may be slightly different than the calculated value because of the stray capacitance inherent in the PCB layout/routing.
2 Vertical driver loads used when characterizing power consumption. Note: actual power depends on the V1 to V4 timing and number of SUBCKs.
V1, V2, V3, V4
6000 pF
SUBCK
1000 pF
500mV TYP
RESET
TRANSIENT
100mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
INPUT SIGNAL CHARACTERISTICS DEFINED AS FOLLOWS:



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