DSP56857 datasheet(140/662 Pages) FREESCALE

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Timing Specifications

5685X Digital Signal Controller User Manual, Rev. 4

5-14

Freescale Semiconductor

5.7 Timing Specifications

5.7.1 Read Timing

5.7.1.1 Consecutive Mode Operation

Figure 5-8 illustrates the read timing for external memory access. For comparison, a single read

cycle is illustrated followed by a null cycle and then a back-to-back read.

Figure 5-8 assumes zero wait states are required for the access. Figure 5-9 illustrates a timing

diagram with one wait state added.

There are two read setup timing parameters for each read cycle. The core will latch the data on

the rising edge of the internal clock while tRSD indicates the core setup time. The external timing

of the address and controls is adjusted so they may be changing at this time. Therefore, a data

latch is introduced to capture the data (at the pin) a quarter clock earlier, on the rising edge of the

internal delayed clock. The setup time required for this latch is illustrated by tRSDP in the

diagrams. For slow clock speeds, tRSDP is more critical, while tRSD may be harder to meet for

faster clock rates.

Note:

During back-to-back reads, RD remains low to provide the fastest read cycle time.

Figure 5-8. External Read Cycle with Clock and RWS = 0

tACCESS

tOHZ

tACCESS

tOEV

tRH

tRL

tCSV

tAV

tCSRH

tCLKA

tRC

Read (RWS = 0)

IDLE

tRSD

tRHD

tRSD

Data In

int_sys_clk

int_sys_clk_delay

A[23:0]

CS[7:0]

RD, OE

D[15:0]

Read (RWS = 0)

tRSDP

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