DSP56857 datasheet(138/662 Pages) FREESCALE

138 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

5-12

Freescale Semiconductor

Figure 5-6. Data Bus Contention Timing Requiring MDAR Field Assertion

5.6.4 Bus Control Register (BCR)

The BCR register defines the default read timing for external memory accesses to addresses not

covered by the CS/CSOR/CSTC registers. The timing specified by the BCR register applies to

both program and data space accesses because the PS and DS control signals are not directly

available on the chip pinouts.

Note:

Any of the CSn signals can be configured to mirror the PS and/or DS function, but then

the associated CSn configuration registers control the timing.

Figure 5-7. Bus Control Register (BCR)

See Programmer’s Sheets on Appendix page C- 12

5.6.4.1 Drive (DRV)—Bit 15

The Drive (DRV) control bit is used to specify what occurs on the external memory port pins

when no external access is performed (whether the pins remain driven or are placed in tri-state).

Table 5-6 summarizes the action of the EMI when the DRV bit is cleared or is set. DRV bit is

cleared on hardware reset, but should be set in most customer applications.

Base + $18

Read

DRV

BMDAR

BWWS

BRWS

Write

Reset

111

tHZOE

tACE

tCS_RAM

tOHZ

tCE

tCS

_FLASH

tCS_FLASH

FLASH READ

Bus CONTENTION

INT_SEMI_CLK

FLASH CS1

FLASH_DATA

RAM CS2

RAM_DATA

Bus Contention with two devices driving data at the same time.

RAM READ

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