DSP56857 datasheet(205/662 Pages) FREESCALE

205 / 662 page

Overview, Rev. 4

Freescale Semiconductor

8-27

Figure 8-14. Fast Interrupt 1 Match Register (FIM1)

See Programmer’s Sheet on Appendix page B - 39

8.7.11.3 Reserved—Bits 15–7

These bits are reserved or not implemented. They are read as 0, but they cannot be modified by

writing.

8.7.11.4 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)

These values are used to declare which two IRQs will be Fast Interrupts. Fast Interrupts vector

directly to a service routine based on values in the Fast Interrupt Vector Address registers without

having to go to a jump table first. IRQs used as Fast Interrupts must be set to priority Level 2.

Unexpected results will occur if a Fast Interrupt vector is set to any other priority. Fast Interrupts

automatically become the highest priority Level 2 Interrupt regardless of their location in the

interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast

Interrupt 1. To determine the vector number of each IRQ. Please refer to Table 8-3.

8.7.12 Fast Interrupt Vector Address Registers (FIVAL0, FIVAH0, FIVAL1,

FIVAH1)

The following four registers are combined to form two, 21-bit vector addresses for the Fast

Interrupts defined in the FIM0 and FIM1 registers.

Figure 8-15. Fast Interrupt 0 Vector Address Low Register (FIVAL0)

See Programmer’s Sheet on Appendix page B - 40

8.7.12.1 Fast Interrupt 0 Vector Address Low—Bits 15–0

Lower 16 bits of Vector Address for Fast Interrupt 0.

Base + $D

Read

FAST INTERRUPT 1

Write

Reset

Base + $B

Read

FAST INTERRUPT 0 VECTOR ADDRESS LOW

Write

Reset

0000

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