AD9670EBZ datasheet(27/48 Pages) AD

27 / 48 page

AD9674

Data Sheet

Rev. A | Page 26 of 47

Tuning is normally off to avoid changing the capacitor settings

during critical times. The tuning circuit is enabled through the

SPI. It is disabled automatically after 512 cycles of the ADC sample

clock. Initializing the tuning of the filter must be performed

after initial power-up and after reprogramming of the filter cutoff

scaling or the ADC sample rate. The tuning is initiated using

Address 0x02B, Bit 6.

Four SPI-programmable settings allow users to vary the high-

pass filter cutoff frequency as a function of the low-pass cutoff

frequency. Two examples are shown in Table 13: an 8 MHz low-

pass cutoff frequency and an 18 MHz low-pass cutoff frequency. In

both cases, as the ratio decreases, the amount of rejection on the

low end frequencies increases. Therefore, making the entire AAF

frequency pass band narrow can reduce low frequency noise or

maximize the dynamic range for harmonic processing.

Table 13. High-Pass Filter Cutoff Options

Addr. 0x02B[1:0]

High-Pass

Filter Cutoff

Ratio1

High-Pass Cutoff Frequency

Low-Pass

Cutoff = 8 MHz

Low-Pass

Cutoff = 18 MHz

00 (default)

670 kHz

1.5 MHz

890 kHz

2.0 MHz

1.33 MHz

3.0 MHz

2.67 MHz

6.0 MHz

Ratio means low-pass filter cutoff frequency/high-pass filter cutoff frequency.

AAF/VGA Test Mode

For debugging and testing, there is a bypass switch to view the

AAF output on the GPO2 and GPO3 pins. This mode can be

enabled via Address 0x109, Bit 4. The differential AAF output

allows only one channel to be accessed at a time. The dc output

voltage is 1.5 V (or AVDD2/2), and the maximum ac output

voltage is 2 V p-p.

ADC

The AD9674 uses a pipelined ADC architecture. The quantized

output from each stage is combined into a 14-bit result in the

digital correction logic. The pipelined architecture permits the

first stage to operate on a new input sample and the remaining

stages to operate on the preceding samples. Sampling occurs on

the rising edge of the clock.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and output clocks.

Clock Input Considerations

For optimum performance, clock the AD9674 sample clock inputs

(CLK+ and CLK−) with a differential signal. This signal is typically

ac-coupled into the CLK+ and CLK− pins via a transformer or

capacitors. These pins are biased internally and require no

additional bias.

Figure 39 shows the preferred method for clocking the AD9674. A

low jitter clock source, such as the Valpey Fisher oscillator, VFAC3-

BHL-50 MHz, is converted from a single-ended configuration

to a differential configuration using an RF transformer.

The back to back Schottky diodes across the secondary transformer

limit clock excursions into the AD9674 to approximately 0.8 V p-p

differential. These diodes help prevent large voltage swings of the

clock from feeding through to other portions of the AD9674, and

they preserve the fast rise and fall times of the signal, which is

critical to low jitter performance.

0.1µF

SCHOTTKY

DIODES:

HSM2812

3.3V

50Ω 100Ω

CLK–

CLK+

ADC

MINI-CIRCUITS®

ADT1-1WT, 1:1Z

XFMR

VFAC3

OUT

Figure 39. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac couple a

differential positive emitter coupled logic (PECL) signal to the

sample clock input pins, as shown in Figure 40. Analog

Devices,Inc., offers a family of clock drivers with excellent jitter

performance,including the AD9516-0, AD9516-1, AD9516-2,

AD9516-3, and AD9516-5 (these five devices are represented by

AD9516-x in Figure 40, Figure 41, and Figure 42), as well as the

AD9524.

0Ω

0.1µF

240Ω

AD9516-x OR AD9524

CLK

*50Ω RESISTOR IS OPTIONAL.

PECL DRIVER

3.3V

OUT

VFAC3

CLK–

CLK+

ADC

50Ω*

Figure 40. Differential PECL Sample Clock

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 41.

100Ω

0.1µF

AD9516-x OR AD9524

CLK

*50Ω RESISTOR IS OPTIONAL.

LVDS DRIVER

3.3V

OUT

VFAC3

CLK–

CLK+

ADC

50Ω*

Figure 41. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

drive CLK+ directly from a CMOS gate, and bypass the CLK− pin

to ground with a 0.1 µF capacitor (see Figure 42).

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