AD9670EBZ datasheet(28/48 Pages) AD

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Data Sheet

AD9674

Rev. A | Page 27 of 47

0.1µF

OPTIONAL

100Ω

0.1µF

CMOS DRIVER

0.1µF

CLK

*50Ω RESISTOR IS OPTIONAL.

AD9516-x OR AD9524

3.3V

OUT

VFAC3

CLK–

CLK+

ADC

50Ω*

Figure 42. Single-Ended 1.8 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs can be

sensitive to the clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9674 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This feature allows a wide

range of clock input duty cycles without affecting the performance

of the AD9674. When the DCS is on, noise and distortion

performance are nearly flat for a wide range of duty cycles.

However, some applications may require the DCS function to

be off. When the DCS function is off, the dynamic range

performance can be affected.

The duty cycle stabilizer uses a delay-locked loop (DLL) to create

the nonsampling edge. As a result, any changes to the sampling

frequency require approximately eight clock cycles to allow the

DLL to acquire and lock to the new rate.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency (fA)

due only to aperture jitter (tJ) can be calculated as follows:

SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)

(7)

In Equation 7, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog

input signal, and ADC aperture jitter (see Figure 43).

Treat the clock input as an analog signal when aperture jitter may

affect the dynamic range of the AD9674. Separate power supplies

for clock drivers from the ADC output driver supplies to avoid

modulating the clock signal with digital noise. Low jitter, crystal

controlled oscillators, such as the Valpey Fisher VFAC3 series,

make the best clock sources. When the clock is generated from

another type of source (by gating, dividing, or other methods),

retime it by the original clock during the last step.

For more information on how jitter performance relates to ADCs,

refer to the AN-501 Application Note and AN-756 Application Note.

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.5ps

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

0.25ps

Figure 43. Ideal SNR vs. Analog Input Frequency and Jitter

Power Dissipation and Power-Down Mode

The power dissipated by the AD9674 is proportional to its sample

rate. The digital power dissipation does not vary significantly

because it is determined primarily by the DRVDD supply and

the bias current of the LVDS output drivers. The AD9674 features

scalable LNA bias currents (see Table 25, Address 0x012). The

default LNA bias current settings are midhigh.

By asserting the PDWN pin high, the AD9674 is placed into

power-down mode. In this state, the device dissipates at a

maximum of 30 mW. During power-down, the LVDS output

drivers are placed into a high impedance state. The AD9674

returns to normal operating mode when the PDWN pin is pulled

low. This pin is only 1.8 V tolerant. To drive the PDWN pin from a

3.3 V logic level, insert a 1 kΩ resistor in series with this pin to

limit the current.

By asserting the STBY pin high, the AD9674 is placed in standby

mode. In this state, the device typically dissipates 630 mW. During

standby, the entire device, except the internal references, powers

down. The LVDS output drivers are placed into a high impedance

state. This mode is well suited for applications that require power

savings because it allows the device to be powered down when

not in use and then to be quickly powered up. In addition, the

time to power up the device is greatly reduced. The AD9674

returns to normal operating mode when the STBY pin is pulled

low. This pin is only 1.8 V tolerant. To drive the STBY pin from

a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to

limit the current.

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