AD9670EBZ datasheet(31/48 Pages) AD

31 / 48 page

AD9674

Data Sheet

Rev. A | Page 30 of 47

Data is clocked out of the AD9674 and must be captured on the

rising and falling edges of DCO±, which support double data

rate (DDR) capturing. The frame clock outputs (FCO±) signal

the start of a new output byte and are equal to the sampling

clock rate.

A 12-, 14-, or 16-bit serial stream can also be initiated from

Address 0x021, Bits[1:0]. The user can implement different serial

streams and test device compatibility with lower and higher

resolution systems using these modes.

When using the SPI, all the data outputs can also invert from

their nominal state by setting Bit 2 in the output mode register

(Address 0x014). This feature is not to be confused with inverting

the serial stream to an LSB first mode. In default mode, as shown in

Figure 2, the MSB is represented first in the data output serial

stream. However, using Address 0x000, Bit 6, this order can be

inverted so that the LSB is represented first in the data output serial

stream.

Digital Output Test Patterns

Nine digital output test pattern options can be initiated through the

SPI using Address 0x0D. These options are useful when validating

receiver capture and timing. See Table 16 for the output test

mode bit sequencing options. Some test patterns have two serial

sequential words and can be alternated in various ways depending

on the test pattern chosen. Note that some patterns may not

adhere to the data format select option. In addition, custom

user defined test patterns can be assigned in the user pattern

registers (Address 0x019 through Address 0x020). All test mode

options except the pseudonoise (PN) sequence short and PN

sequence long can support 8- to 14-bit word lengths to verify

data capture to the receiver.

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 29 − 1 bits, or 511 bits. A

description of the PN sequence short pattern and how it is

generated can be found in Section 5.1 of the ITU-T O.150 (05/96)

standard. However, the PN sequence long pattern differs from

the ITU-T O.150 (05/96) standard because it begins with a specific

value instead of 1s (see Table 15 for the initial values).

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 223 − 1 bits, or 8,388,607 bits.

A description of the PN sequence long pattern and how it is

generated can be found in Section 5.6 of the ITU-T O.150 (05/96)

standard. The PN sequence long pattern differs from the standard,

however, because the starting value of the pattern is a specific

value rather than a value of only 1s and the AD9674 inverts the

bit stream (see Table 15 for the initial values). The output sample

size depends on the selected bit length.

Table 15. PN Sequence Initial Values

Sequence

Initial

Value

First Three Output Samples

(MSB First, 16-Bit)

PN Sequence Short

0x092

0x496F, 0xC9A9, 0x980C

PN Sequence Long

0x003

0xFF5C, 0x0029, 0xB80A

See the Memory Map section for information on how to change

these additional digital output timing features through the SPI.

SDIO Pin

The SDIO pin is required to operate the SPI. The pin has an

internal 30 kΩ pull-down resistor that pulls this pin low and is only

1.8 V tolerant. If applications require that this pin be driven

from a 3.3 V logic level, insert a 1 kΩ resistor in series with this

pin to limit the current.

SCLK Pin

The SCLK pin is required to operate the SPI. The pin has an

internal 30 kΩ pull-down resistor that pulls this pin low and is

only 1.8 V tolerant. To drive the SCLK pin from a 3.3 V logic

level, insert a 1 kΩ resistor in series with this pin to limit the

current.

CSB Pin

The CSB pin is required to operate the SPI. The pin has an

internal 70 kΩ pull-up resistor that pulls this pin high and is

only 1.8 V tolerant. To drive the CSB pin from a 3.3 V logic

level, insert a 1 kΩ resistor in series with this pin to limit the

current.

RBIAS Pin

To set the internal core bias current of the ADC, place a resistor

nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a

resistor other than the recommended 10.0 kΩ resistor for RBIAS

degrades the performance of the device. Therefore, it is imperative

that at least a 1% tolerance on this resistor be used to achieve

consistent performance.

VREF Pin

A stable and accurate 0.5 V voltage reference is built into the

AD9674. This voltage reference is gained up internally by a factor

of 2, setting VREF to 1.0 V, which results in a full-scale differential

input span of 2.0 V p-p for the ADC. VREF is set internally by

default, but the VREF pin can be driven externally with a 1.0 V

reference to achieve more accuracy. However, the AD9674 does

not support ADC full-scale ranges less than 2.0 V p-p.

When applying the decoupling capacitors to the VREF pin, use

ceramic, low equivalent series resistance (ESR) capacitors. Ensure

that these capacitors are close to the reference pin and on the same

layer of the PCB as the AD9674. The VREF pin must have both

a 0.1 µF capacitor and a 1 µF capacitor that are connected in

parallel to the analog ground. These capacitor values are recom-

mended for the ADC to properly settle and acquire the next valid

sample.

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