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AD9670EBZ датащи(PDF) 36 Page - Analog Devices |
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AD9670EBZ датащи(HTML) 36 Page - Analog Devices |
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36 / 48 page ![]() Data Sheet AD9674 Rev. A | Page 35 of 47 DIGITAL BLOCK POWER SAVING SCHEME To reduce power consumption in the digital block after the ADC, the RF decimator and filter start in an idle state after running the chip (Register 0x008, Bits[2:0] = 000). The digital block only switches to a running state when the negative edge of the TX_TRIG signal pulse is detected, or with a software TX_TRIG signal write (Register 0x10C, Bit 5 = 1). To put the digital block back into the idle state (while the rest of the chip is still running) and save power, raise the TX_TRIG signal high or write to the profile index (Register 0x10C, Bits[0:4]). The digital block will also switch to the idle state if the power stop expires when using the advanced power control feature. Figure 52 illustrates the digital block power saving scheme. CHIP IN POWER-DOWN, STANDBY, OR CW MODE DIGITAL DECIMATOR/FILTER IDLE DIGITAL DECIMATOR/FILTER RUNNING RUN CHIP NEGATIVE EDGE TX_TRIG OR SOFTWARE TX_TRIG TX_TRIG IS HIGH, PROFILE INDEX WRITE, OR POWER STOP EXPIRES Figure 52. Digital Block Power Saving Scheme |
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