AD9670EBZ datasheet(35/48 Pages) AD

35 / 48 page

AD9674

Data Sheet

Rev. A | Page 34 of 47

RF DECIMATOR

The input to the RF decimator is either the ADC output data or

a test waveform, as described in the Digital Test Waveforms section.

The test waveforms are enabled per channel using Address 0x11A

(see Table 25).

DC Offset Calibration

DC offset can be reduced through a manual system calibration

process. The dc offset of every channel in the system is measured,

followed by setting a calibration value in Address 0x110 and

Address 0x111. Note that these registers are both chip and local

addresses, meaning the registers are accessed using the chip address

and device index. The dc offset calibration can be bypassed

using Address 0x10F, Bits[2:0].

Multiband AAF and Decimate by 2

The multiband filter is a finite impulse response (FIR) filter. It is

programmable with low or high band filtering. The filter requires

11 input samples to populate the filter. The decimation rate is fixed

at 2×. Therefore, the decimation frequency is fDEC = fSAMPLE/2.

Figure 50 and Figure 51 show the frequency response of the filter,

depending on this mode. Figure 50 shows the attenuation amp-

litude over the Nyquist frequency range. Figure 51 shows the

pass band response as nearly flat.

–60

FREQUENCY (MHz)

–50

–40

–30

–20

–10

LOW BAND FILTER

HIGH BAND FILTER

Figure 50. AAF Frequency Response

(Frequency Scale Assumes fADC = 2 × fDEC = 40 MHz)

–8

FREQUENCY (MHz)

LOW BAND FILTER

HIGH BAND FILTER

–7

–6

–5

–4

–3

–2

–1

Figure 51. AAF Frequency Response Zoomed In

(Frequency Scale Assumes fADC = 2 × fDEC = 40 MHz)

High-Pass Filter

A second-order Butterworth, high-pass, infinite impulse response

(IIR) filter can be applied after the RF decimator. The IIR filter

has a settling time of 2.5 µs and a cutoff frequency of 700 kHz

for an encode clock of 50 MHz. Therefore, if the ADC clock is

50 MHz, the first 125 samples (2.5 µs/0.02 µs) must be ignored.

The filter can be bypassed or enabled in the vector profile if the

filter is enabled using Address 0x113, Bit 5. If the filter is

bypassed by setting Address 0x113, Bit 5, to 1, the filter cannot

be enabled from the vector profile.

DIGITAL TEST WAVEFORMS

Digital test waveforms can be used in the digital processing block

instead of the ADC output. To enable digital test waveforms,

use Address 0x11B. Each channel can be individually enabled in

Address 0x11A.

Waveform Generator

For testing and debugging, a programmable waveform generator

can be used in place of ADC data. The waveform generator can

vary offset, amplitude, and frequency. The generator uses the ADC

sample frequency, fSAMPLE, and ADC full-scale amplitude, AFULL-SCALE,

as references. The values are set in Address 0x117, Address 0x118,

and Address 0x119 (see Table 25).

x = C + A × sin(2 × π × N)

(8)

SAMPLE ×

, see Address 0x117

(9)

SCALE

FULL

−

, see Address 0x118

(10)

C = AFULL-SCALE × a × 2−(13− b), see Address 0x119

(11)

Channel ID and Ramp Generator

In Channel ID test mode, the output is a concatenated value.

Bits[6:0] are a ramp. Bit 7 is reserved as 0. Bits[10:8] are the

channel ID such that Channel A is coded as 000 and Channel B

is 001. Bits[15:11] compose the chip address.

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