AD9670EBZ datasheet(29/48 Pages) AD

29 / 48 page

AD9674

Data Sheet

Rev. A | Page 28 of 47

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, phase-locked loop

(PLL), and biasing networks. The decoupling capacitors on VREF

are discharged when entering power-down mode and must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in power-down mode:

shorter cycles result in proportionally shorter wake-up times. To

restore the device to full operation, approximately 375 µs is

required when using the recommended 1 µF and 0.1 µF dec-

oupling capacitors on the VREF pin and the 0.01 µF decoupling

capacitors on the GAIN± pins. Most of this time is dependent on

gain decoupling; higher value decoupling capacitors on the

GAIN± pins result in longer wake-up times.

Other power-down options are available when using the SPI port

interface. The user can individually power down each channel or

place the entire device into standby mode. When fast wake-up

times are required, standby mode allows the user to keep the

internal PLL powered up. The wake-up time is slightly dependent

on gain. To achieve a 2 µs wake-up time when the device is in

standby mode, apply 0.8 V to the GAIN± pins.

Power and Ground Connection Recommendations

When connecting power to the AD9674, use two separate 1.8 V

supplies: one for analog (AVDD1) and one for digital (DRVDD).

When only one 1.8 V supply is available, route it to the AVDD1

pin first, tap it off, and isolate it with a ferrite bead or a filter

choke preceded by decoupling capacitors for the DRVDD pin.

The DVDD pin can be tied to the 1.8 V DRVDD supply. When

this is done, route the DVDD supply first, tap it off, and isolate it

with a ferrite bead or filter choke preceded by decoupling

capacitors for the DRVDD pin. It is not recommended to use the

same supply for AVDD1, DVDD, and DRVDD to avoid noise

issues. For compatibility with the AD9674 or for lower power

operation, the DVDD pin can be tied to 1.4 V.

To cover both high and low frequencies, use several decoupling

capacitors on all supplies. Locate these capacitors close to the

point of entry at the PCB level and close to the device, with

minimal trace lengths.

When using the AD9674, a single PCB ground plane is sufficient.

With proper decoupling and smart partitioning of the analog,

digital, and clock sections of the PCB, optimum performance is

easily achievable.

Advanced Power Control

For an ultrasound system, not all channels are needed during all

scanning periods. The POWER_START and POWER_STOP

values in the vector profile can be used to delay the channel

startup and turn the channel off after a certain number of samples.

These counters are relative to TX_TRIG±. The analog circuitry

must power up before the digital circuitry. The analog circuitry

must power up (POWER_SETUP) before POWER_START is

set up in Register 0x112 (see Table 25).

TX_TRIG±

POWER_STOP

(PROFILE SPECIFIC)

POWER_START

(PROFILE SPECIFIC)

POWER_SETUP

(SPI SET)

DIGITAL

POWER

ANALOG

POWER

Figure 44. Power Sequencing

Digital Outputs and Timing

The AD9674 differential outputs conform to the ANSI-644

LVDS standard on default power-up. This setting can be

changed to a low power, reduced signal option similar to the

IEEE 1596.3 standard via the SPI using Address 0x015, Bit 7.

This LVDS standard can further reduce the overall power

dissipation of the device by approximately 36 mW.

The LVDS driver current is derived on chip and sets the output

current at each output equal to a nominal 3.5 mA. A 100 Ω

differential termination resistor placed at the LVDS receiver

inputs results in a nominal 350 mV swing at the receiver.

The AD9674 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capability

for superior switching performance in noisy environments. Single

point to point network topologies are recommended with a 100 Ω

termination resistor placed as close to the receiver as possible.

No far-end receiver termination and poor differential trace routing

may result in timing errors. The trace length must be no longer

than 24 inches; keep the differential output traces close together

and at equal lengths.

Figure 45 and Figure 46 show an example of the LVDS output

using the ANSI-644 standard (default) data eye and a time interval

error (TIE) jitter histogram with trace lengths of less than 24 inches

on standard FR-4 material. Figure 47 and Figure 48 show an

example of the trace lengths exceeding 24 inches on standard

FR-4 material. Notice that the TIE jitter histogram reflects the

decrease of the data eye opening as the edge deviates from the

ideal position. Therefore, the user must determine whether the

waveforms meet the timing budget of the design when the trace

lengths exceed 24 inches.

AD9670EBZ датащи(PDF) 29 Page - Analog Devices

AD9670EBZ датащи(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL