AD9670EBZ datasheet(30/48 Pages) AD

30 / 48 page

Data Sheet

AD9674

Rev. A | Page 29 of 47

400

–200

200

300

–100

100

–400

–300

–1.5ns

–0.5ns

–1.0ns

0ns

0.5ns

1.0ns

1.5ns

EYE: ALL BITS

ULS: 11197/11197

Figure 45. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

of Less Than 24 Inches on Standard FR-4

–150ps

–100ps

–50ps

0ps

100ps

50ps

150ps

Figure 46. TIE Jitter Histogram for LVDS Outputs in ANSI-644 Mode with

Trace Lengths of Less Than 24 Inches on Standard FR-4

400

–200

–300

200

300

–100

100

–400

–1.5ns

–0.5ns

–1.0ns

0ns

0.5ns

1.0ns

1.5ns

ULS: 11199/11199

EYE: ALL BITS

Figure 47. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

of Greater Than 24 Inches on Standard FR-4

–300ps

–200ps

–100ps

0ps

200ps

100ps

300ps

Figure 48. TIE Jitter Histogram for LVDS Outputs in ANSI-644 Mode with

Trace Lengths of Greater Than 24 Inches on Standard FR-4

Additional SPI options let the user further increase the internal

current of all eight outputs to drive longer trace lengths. Even

though this produces sharper rise and fall times on the data edges,

increasing the internal current is less prone to bit errors and

improves frequency distribution. The power dissipation of the

DRVDD supply increases when this option is used.

In applications that require increased drive current, Address 0x015

allows the user to adjust the drivers from 2 mA to 3.72 mA. Note

that this feature requires Bit 3 of Address 0x015 to be set to 1. The

drive current can be adjusted for both ANSI-644 and IEEE 1596.3

(low power) mode. See Table 25 for more details.

The format of the output data is twos complement by default.

Table 14 provides an example of the output coding format. To

change the output data format to twos complement, see the

Memory Map section.

Table 14. Digital Output Coding with RF Decimator Bypassed,

Digital HPF Bypassed

Code

(VIN+) − (VIN−),

Input Span = 2 V p-p (V)

Digital Output Mode: Twos

Complement (D13 to D0)

16384

+1.00

01 1111 1111 1111

8192

0.00

00 0000 0000 0000

8191

−0.000488

11 1111 1111 1111

−1.00

10 0000 0000 0000

Digital data from each channel is serialized based on the number

of lanes that are enabled (see Table 25). The maximum data rate

for each serial output lane is 1 Gbps. For one channel per lane with

a 14-bit data stream and ADC sample clock of 70 MHz, the output

data rate is 980 Mbps (14 bits × 70 MHz = 980 Mbps) with the

RF decimator bypassed, and digital HPF bypassed. For higher

sample rates, enabling the RF decimator is required.

Two output clocks are provided to assist in capturing data from

the AD9674. The digital clock outputs (DCO±) are used to clock

the output data and are equal to seven times the sampling clock

rate in 14-bit mode with the RF decimator bypassed and digital

HPF bypassed.

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