AD9670EBZ datasheet(15/48 Pages) AD

15 / 48 page

AD9674

Data Sheet

Rev. A | Page 14 of 47

Pin No.

Mnemonic

Description

L11

DOUTA+

ADC Channel A Digital Output True.

K11

STBY

Standby Power-Down.

J11

PDWN

Full Power-Down.

K12

SCLK

Serial Clock.

J12

SDIO

Serial Data Input/Output.

H12

CSB

Chip Select Bar.

LG-A

LNA Ground for Channel A.

LI-A

LNA Analog Input for Channel A.

LOSW-A

LNA Analog Switched Output for Channel A.

LO-A

LNA Analog Inverted Output for Channel A.

B10

LG-B

LNA Ground for Channel B.

A10

LI-B

LNA Analog Input for Channel B.

D10

LOSW-B

LNA Analog Switched Output for Channel B.

C10

LO-B

LNA Analog Inverted Output for Channel B.

B11

LG-C

LNA Ground for Channel C.

A11

LI-C

LNA Analog Input for Channel C.

D11

LOSW-C

LNA Analog Switched Output for Channel C.

C11

LO-C

LNA Analog Inverted Output for Channel C.

B12

LG-D

LNA Ground for Channel D.

A12

LI-D

LNA Analog Input for Channel D.

D12

LOSW-D

LNA Analog Switched Output for Channel D.

C12

LO-D

LNA Analog Inverted Output for Channel D.

K10

GPO0

General-Purpose Open-Drain Output 0.

J10

GPO1

General-Purpose Open-Drain Output 1.

GPO2

General-Purpose Open-Drain Output 2.

GPO3

General-Purpose Open-Drain Output 3.

RESET−

Synchronizing Input for LO Divide-by-M Counter Complement.

RESET+

Synchronizing Input for LO Divide-by-M Counter True.

MLO−

CW Doppler Multiple Local Oscillator Input Complement.

MLO+

CW Doppler Multiple Local Oscillator Input True.

GAIN−

Gain Control Voltage Input Complement.

GAIN+

Gain Control Voltage Input True.

RBIAS

External Resistor to Set the Internal ADC Core Bias Current.

VREF

Voltage Reference Input/Output.

CWI−

CW Doppler I Output Complement.

CWI+

CW Doppler I Output True.

CWQ−

CW Doppler Q Output Complement.

CWQ+

CW Doppler Q Output True.

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