Data Sheet

AD9674

Rev. A | Page 39 of 47

Table 24. SPI Write Start-Up Sequence Example

1

Setting the profile index requires an additional SPI write in SPI MSB mode before the chip runs to complete the current profile buffer update.

2

Running the chip from full power-down mode requires 375 µs wake-up time, as listed in Table 3.

3

Software TX_TRIG switches the demodulator/decimator digital block to a running state. The software TX_TRIG signal may not be needed if a hardware TX_TRIG signal

is used to run the digital block.

4

Tuning the filters requires 512 ADC clock cycles.

Address

Value

Description

0x000

0x3C

Initiates SPI reset

0x002

0x0X (default)

Sets speed mode to 40 MHz

0x0FF

0x01

Enables speed mode change (required after Register 0x002 writes)

0x004

0x0F

Sets local registers to all channels

0x005

0x3F

Sets local registers to all channels

0x113

0x00

Bypasses RF decimator; enable digital HPF

0x011

0x06 (default)

Sets LNA gain = 21.6 dB, VGA gain = external, and PGA gain = 24 dB

0xF00

0xFF

Continuous run mode enabled; do not power down channels (POWER_STOP LSB)

0xF01

0x7F

Continuous run mode enabled; do not power down channels (POWER_STOP MSB)

0xF02

0x00

Powers up all channels 0 clock cycles after TX_TRIG± (POWER_STOP LSB)

0xF03

0x80

Digital high-pass bypassed (POWER_STOP MSB)

0x00 (default)

Sets the profile index (required after profile memory writes)

0x014

0x00

Sets output data format

0x008

0x00

0x021

0x05

14 bits, 8 lanes, frame clock output (FCO) covers entire frame

0x199

0x80

Enables automatic clocks per sample calculation

0x19B

0x50

Serial format

0x188

0x01

Enables start code

0x18B

0x27

Sets start code MSB

0x18C

0x72

Sets start code LSB

0x182

0x82

Autoconfigures PLL

0x20

Sets SPI TX_TRIG and profile index

0x00F

0x18 (default)

Sets low-pass filter cutoff frequency and bandwidth mode

0x02B

0x40