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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9670EBZ датащи(PDF) 32 Page - Analog Devices |
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AD9670EBZ датащи(HTML) 32 Page - Analog Devices |
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32 / 48 page  Data Sheet AD9674 Rev. A | Page 31 of 47 Table 16. Flexible Output Test Modes OutputTest Mode Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Subject to Resolution Select 0000 Off (default) Not applicable Not applicable Not applicable 0001 Midscale short 10 0000 0000 0000 Same Yes 0010 Positive full-scale short 11 1111 1111 1111 Same Yes 0011 Negative full-scale short 00 0000 0000 0000 Same Yes 0100 Checkerboard 10 1010 1010 1010 01 0101 0101 0101 No 0101 PN sequence long Not applicable Not applicable Yes 0110 PN sequence short Not applicable Not applicable Yes 0111 One-word/zero-word toggle 11 1111 1111 1111 00 0000 0000 0000 No 1000 User input Address 0x019 and Address 0x01A Address 0x01B and Address 0x01C No 1111 Ramp output 00 0000 0000 0000 00 0000 0000 0001 Yes General-Purpose Output Pins The general-purpose output pins, GPO0, GPO1, GPO2 and GPO3, can be used in a system to provide programmable inputs to other chips in the system. The value of each pin is set via Address 0x00E to either Logic 0 or Logic 1 (see Table 25). Chip Address Pins The chip address pins can be used to address individual AD9674 chips among multiple chips in a system. The chip address mode is enabled using Address 0x115, Bit 5 (see Table 25). If the value written to Bits[4:0] matches the value on the chip address bit pins (ADDR4 to ADDR0]), the device is selected and any subsequent SPI writes or reads to addresses indicated as chip registers are written only to that device. If chip address mode is disabled, all addresses can be written to regardless of the value on the address pins. ANALOG TEST SIGNAL GENERATION The AD9674 can generate analog test signals that can be switched to the input of the LNA of each channel to be used for channel gain calibration. The test signal amplitude at the LNA output is dependent on LNA gain, as shown in Table 17. Table 17. Test Signal Fundamental Amplitude at LNA Output Address 0x116, Bits[3:2], Analog TestTones LNA Gain 15.6 dB LNA Gain 17.9 dB LNA Gain 21.6 dB 00 (default) 80 mV p-p 98 mV p-p 119 mV p-p 01 160 mV p-p 196 mV p-p 238 mV p-p 10 320 mV p-p 391 mV p-p 476 mV p-p The test signal amplitude at the input to the ADC can be calculated given the LNA gain, attenuator control voltage, and the PGA gain. Table 18 and Table 19 give example calculations. Table 18. Test Signal Fundamental Amplitude at ADC Input, VGAIN = 0 V, PGA Gain = 21 dB Address 0x116, Bits[3:2], Analog TestTones LNA Gain 15.6 dB LNA Gain 17.9 dB LNA Gain 21.6 dB 00 (default) −29 dBFS −28 dBFS −26 dBFS 01 −23 dBFS −22 dBFS −20 dBFS 10 −17 dBFS −16 dBFS −14 dBFS Table 19. Test Signal Fundamental Amplitude at ADC Input, VGAIN = 0 V, PGA Gain = 30 dB Address 0x116, Bits [3:2], Analog Test Tones LNA Gain 15.6 dB LNA Gain 17.9 dB LNA Gain 21.6 dB 00 (default) −20 dBFS −19 dBFS −17 dBFS 01 −14 dBFS −13 dBFS −11 dBFS 10 −8 dBFS −7 dBFS −5 dBFS |
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