AD9670EBZ datasheet(41/48 Pages) AD

41 / 48 page

Data Sheet

AD9674

Rev. A | Page 40 of 47

Table 25. Memory Map Registers

Addr.

(Hex) RegisterName

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value Comments

ChipConfigurationRegisters

0x000 CHIP_PORT_

CONFIG

LSB first:

0 = off

(default),

1 = on

SPI reset:

0 = off

(default),

1 = on

SPI reset:

0 = off

(default),

1 = on

LSB first:

0 = off

(default),

1 = on

0x18

Mirror nibbles so LSB first

or MSB Mode I is set

correctly regardless of

shift mode. SPI reset

reverts all registers

(including LVDS registers),

except Register 0x000, to

their default values, and

Bit 5 bits automatically

clear.

f0x001 CHIP_ID

Chip ID, Bits[7:0] (AD9674 = 0xA8), default

0xA8

Default is unique chip ID,

different for each device;

read only register.

0x002 CHIP_GRADE

Speed mode, Bits[5:4]

(identify device

variants of chip ID):

00 = Mode I

(40 MSPS) (default),

01 = Mode II (65 MSPS),

10 = Mode III (80 MSPS),

11 = Mode III (125 MSPS)

0x0X

Speed mode used to

differentiate ADC speed

power modes (must

update Register 0x0FF after

for the speed mode

changes to take effect).

0x0FF DEVICE_UPDATE

0x00

A write to Register 0x0FF

(value does not matter)

resets all default register

values (analog and ADC

registers only; not

JESD204B ones and not

previously written since

the last reset/load of

defaults.

0x004 DEVICE_INDEX_2 X

Data

Channel H:

0 = off,

1 = on

(default)

Data

Channel G:

0 = off,

1 = on

(default)

Data

Channel F:

0 = off,

1 = on

(default)

Data

Channel E:

0 = off,

1 = on

(default)

0x0F

Bits are set to determine

which on-chip channel

receives the next write

command.

0x005 DEVICE_INDEX_1 X

Clock

Channel

DCO±:

0 = off,

1 = on

(default)

Clock

Channel

FCO±:

0 = off,

1 = on

(default)

Data

Channel D:

0 = off,

1 = on

(default)

Data

Channel C:

0 = off,

1 = on

(default)

Data

Channel B:

0 = off,

1 = on

(default)

Data

Channel A:

0 = off,

1 = on

(default)

0x3F

Bits are set to determine

which on-chip channel

receives the next write

command.

0x008 GLOBAL_MODES X

LNA input

impedance:

0 = 6 kΩ

(default),

1 = 3 kΩ

Internal power-down mode:

000 = chip run (TGC mode),

001 = full power-down (default),

010 = standby,

011 = reset all LVDS registers,

100 = CW Doppler mode

(TGC is powered down)

0x01

Determines generic

modes of chip operation

(global).

0x009 GLOBAL_CLOCK X

DCS:

0 = off,

1 = on

(default)

0x01

Turns the internal DCS on

and off (global).

0x00A PLL_STATUS

PLL lock status:

0 = not locked

(default),

1 = locked

0x00

Monitor PLL lock status

(read only, global).

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