MPC7450EC datasheet(3/52 Pages) MOTOROLA

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MPC7450 RISC Microprocessor Hardware Speciﬁcations

Features

1.2

Features

This section summarizes features of the MPC7450 implementation of the PowerPC architecture. Major

features of the MPC7450 are as follows:

Major features of the MPC7450 are as follows:

•

High-performance, superscalar microprocessor

— As many as 4 instructions can be fetched from the instruction cache at a time

— As many as 3 instructions can be dispatched to the issue queues at a time

— As many as 12 instructions can be in the instruction queue (IQ)

— As many as 16 instructions can be at some stage of execution simultaneously

— Single-cycle execution for most instructions

— One instruction per clock cycle throughput for most instructions

— Seven-stage pipeline control

•

Eleven independent execution units and three register ﬁles

— Branch processing unit (BPU) features static and dynamic branch prediction

– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a

cache of branch instructions that have been encountered in branch/loop code sequences. If

a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner

than it can be made available from the instruction cache. Typically, a fetch that hits the

BTIC provides the ﬁrst four instructions in the target stream.

– 2048-entry branch history table (BHT) with two bits per entry for four levels of

prediction—

not-taken, strongly not-taken, taken, strongly taken

– Up to three outstanding speculative branches

– Branch instructions that do not update the count register (CTR) or link register (LR) are

often removed from the instruction stream.

– 8-entry link register stack to predict the target address of Branch Conditional to Link

— Four integer units (IUs) that share 32 GPRs for integer operands

– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except

multiply, divide, and move to/from special-purpose register instructions.

– IU2 executes miscellaneous instructions including the CR logical operations, integer

multiplication and division instructions, and move to/from special-purpose register

instructions.

— Five-stage FPU and a 32-entry FPR ﬁle

– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations

– Supports non-IEEE mode for time-critical operations

– Hardware support for denormalized numbers

– Thirty-two 64-bit FPRs for single- or double-precision operands

— Four vector units and 32-entry vector register ﬁle (VRs)

– Vector permute unit (VPU)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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