MPC7450EC datasheet(22/52 Pages) MOTOROLA

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MPC7450 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Table 12 provides the L3 bus interface AC timing speciﬁcations for the conﬁguration as shown in Figure 9,

assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8.

Table 12. L3 Bus Interface AC Timing Speciﬁcations for MSUG2

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Speed Grades

Unit

Notes

Min

Max

L3_CLK rise and fall time

tL3CR and tL3CF

—

1.0

Setup times:Data and parity

tL3DVEH and tL3DVEL

–(tL3_ECHO_CLK/4

– 0.35)

—

2, 3, 4

Input hold times:Data and parity

tL3DXEH and tL3DXEL

tL3_ECHO_CLK/4

+ 0.35

—

2, 4

Valid times:Data and parity

All other outputs

tL3CHDV and tL3CLDV

tL3CHOV

—

–tL3_CLK/4 + 0.5

tL3_CLK/4 + 1.0

5, 6, 7

5, 7

Output hold times:

Data and parity

All other outputs

tL3CHDX and tL3CLDX

tL3CHOX

tL3_CLK/4 – 0.35

tL3_CLK/4 + 0.5

—

5, 6, 7

5, 7

L3_CLK to high impedance:

Data and parity

All other outputs

tL3CLDZ

tL3CHOZ

—

tL3_CLK/2

tL3_CLK/4 + 2.0

Notes:

1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.

2. For DDR, all input speciﬁcations are measured from the midpoint of the signal in question to the midpoint voltage

of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.

3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency

with other input setup time speciﬁcations, this will be treated as negative input setup time.

4. tL3_ECHO_CLK/4 is one-fourth the period of L3_ECHO_CLKn. This parameter indicates that the MPC7450 can latch

an input signal that is valid for only a short time before and a short time after the midpoint between the rising and

falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency.

5. All output speciﬁcations are measured from the midpoint voltage of the rising (or for DDR write data, also the

falling) edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All

output timings assume a purely resistive 50-

Ω load (see Figure 8).

6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10. For consistency with other

output valid time speciﬁcations, this will be treated as negative output valid time.

7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the speciﬁed output signal is actually

launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output

valid and output hold times such that the speciﬁed output signal will be valid for approximately one L3_CLK period

starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock

period after the edge it will be sampled.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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