MPC7450EC datasheet(17/52 Pages) MOTOROLA

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MOTOROLA

MPC7450 RISC Microprocessor Hardware Speciﬁcations

Electrical and Thermal Characteristics

Figure 4 provides the AC test load for the MPC7450.

Figure 4. AC Test Load

SYSCLK to ARTRY/SHD0/SHD1 high impedance after

precharge

tKHARPZ

—2

sysclk

5, 8,

9, 10

Notes:

All input speciﬁcations are measured from the midpoint of the signal in question to the midpoint of the rising edge

of the input SYSCLK. All output speciﬁcations are measured from the midpoint of the rising edge of SYSCLK to

the midpoint of the signal in question. All output timings assume a purely resistive 50-

Ω load (see Figure 4). Input

and output timings are measured at the pin; time-of-ﬂight delays must be added for trace lengths, vias, and

connectors in the system.

The symbology used for timing speciﬁcations herein follows the pattern of t(signal)(state)(reference)(state) for inputs

and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid

state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV

symbolizes the time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold

time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH)

(note the position of the reference and its state for inputs) and output hold time can be read as the time from the

rising edge (KH) until the output went invalid (OX).

The setup and hold time is with respect to the rising edge of HRESET (see Figure 5).

This speciﬁcation is for conﬁguration mode select only.

tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be

multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

Mode select signals are: BVSEL, L3VSEL, PLL_CFG[0:3], PLL_EXT, BMODE[0:1].

According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then

precharged high before returning to high impedance as shown in Figure 6. The nominal precharge width for TS is

0.5

× t

SYSCLK, i.e., less than the minimum tSYSCLK period, to ensure that another master asserting TS on the

following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal

asserted. Output valid time is tested for precharge.The high impedance behavior is guaranteed by design.

According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period

immediately following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving

it low. Any master asserting it low in the ﬁrst clock following AACK will then go to high impedance for one clock

before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for

ARTRY is 1.0 tsysclk; that is, it should be high impedance as shown in Figure 6 before the ﬁrst opportunity for

another master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The

high-impedance behavior is guaranteed by design.

According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle

of TS. Timing is the same as ARTRY, i.e., the signal is high impedance for a fraction of a cycle, then negated for

up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge

width for SHD0 and SHD1 is 1.0 tsysclk. The edges of the precharge vary depending on the programmed ratio of

core to bus (PLL conﬁgurations).

10. Guaranteed by design and not tested.

Table 9. Processor Bus AC Timing Speciﬁcations (continued)

At recommended operating conditions. See Table 4.

Parameter

Symbol2

All Speed Grades

Unit

Notes

Min

Max

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

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INC

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